arch/arm/boot/dts/am335x-sancloud-bbe-common.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
   4  */
   5
   6 &am33xx_pinmux {
   7         cpsw_default: cpsw_default {
   8                 pinctrl-single,pins = <
   9                         /* Slave 1 */
  10                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT_PULLDOWN, MUX_MODE2)   /* mii1_txen.rgmii1_tctl */
  11                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE2)    /* mii1_rxdv.rgmii1_rctl */
  12                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd3.rgmii1_td3 */
  13                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd2.rgmii1_td2 */
  14                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd1.rgmii1_td1 */
  15                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT_PULLDOWN, MUX_MODE2)    /* mii1_txd0.rgmii1_td0 */
  16                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_OUTPUT_PULLDOWN, MUX_MODE2)  /* mii1_txclk.rgmii1_tclk */
  17                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE2)   /* mii1_rxclk.rgmii1_rclk */
  18                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd3.rgmii1_rd3 */
  19                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd2.rgmii1_rd2 */
  20                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd1.rgmii1_rd1 */
  21                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE2)     /* mii1_rxd0.rgmii1_rd0 */
  22                 >;
  23         };
  24
  25         cpsw_sleep: cpsw_sleep {
  26                 pinctrl-single,pins = <
  27                         /* Slave 1 reset value */
  28                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_INPUT_PULLDOWN, MUX_MODE7)
  29                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_DV, PIN_INPUT_PULLDOWN, MUX_MODE7)
  30                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
  31                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
  32                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
  33                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
  34                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
  35                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_CLK, PIN_INPUT_PULLDOWN, MUX_MODE7)
  36                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD3, PIN_INPUT_PULLDOWN, MUX_MODE7)
  37                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD2, PIN_INPUT_PULLDOWN, MUX_MODE7)
  38                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE7)
  39                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE7)
  40                 >;
  41         };
  42
  43         usb_hub_ctrl: usb_hub_ctrl {
  44                 pinctrl-single,pins = <
  45                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_OUTPUT_PULLUP, MUX_MODE7)     /* rmii1_refclk.gpio0_29 */
  46                 >;
  47         };
  48 };
  49
  50 &mac_sw {
  51         pinctrl-0 = <&cpsw_default>;
  52         pinctrl-1 = <&cpsw_sleep>;
  53 };
  54
  55 &cpsw_port1 {
  56         phy-mode = "rgmii-id";
  57 };
  58
  59 &i2c0 {
  60         usb2512b: usb-hub@2c {
  61                 pinctrl-names = "default";
  62                 pinctrl-0 = <&usb_hub_ctrl>;
  63                 compatible = "microchip,usb2512b";
  64                 reg = <0x2c>;
  65                 reset-gpios = <&gpio0 29 GPIO_ACTIVE_LOW>;
  66         };
  67 };