arch/arm/boot/dts/am335x-phycore-som.dtsi

   1 // SPDX-License-Identifier: GPL-2.0-only
   2 /*
   3  * Copyright (C) 2015 Phytec Messtechnik GmbH
   4  * Author: Teresa Remmet <t.remmet@phytec.de>
   5  */
   6
   7 #include "am33xx.dtsi"
   8 #include <dt-bindings/interrupt-controller/irq.h>
   9
  10 / {
  11         model = "Phytec AM335x phyCORE";
  12         compatible = "phytec,am335x-phycore-som", "ti,am33xx";
  13
  14         aliases {
  15                 rtc0 = &i2c_rtc;
  16                 rtc1 = &rtc;
  17         };
  18
  19         cpus {
  20                 cpu@0 {
  21                         cpu0-supply = <&vdd1_reg>;
  22                 };
  23         };
  24
  25         memory@80000000 {
  26                 device_type = "memory";
  27                 reg = <0x80000000 0x10000000>; /* 256 MB */
  28         };
  29
  30         vcc5v: fixedregulator0 {
  31                 compatible = "regulator-fixed";
  32                 regulator-name = "vcc5v";
  33                 regulator-min-microvolt = <5000000>;
  34                 regulator-max-microvolt = <5000000>;
  35                 regulator-boot-on;
  36                 regulator-always-on;
  37         };
  38 };
  39
  40 /* Crypto Module */
  41 &aes {
  42         status = "okay";
  43 };
  44
  45 &sham {
  46         status = "okay";
  47 };
  48
  49 /* EMMC */
  50 &am33xx_pinmux {
  51         emmc_pins: pinmux_emmc_pins {
  52                 pinctrl-single,pins = <
  53                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN1, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn1.mmc1_clk */
  54                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN2, PIN_INPUT_PULLUP, MUX_MODE2)       /* gpmc_csn2.mmc1_cmd */
  55                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad0.mmc1_dat0 */
  56                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad1.mmc1_dat1 */
  57                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad2.mmc1_dat2 */
  58                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad3.mmc1_dat3 */
  59                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad4.mmc1_dat4 */
  60                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad5.mmc1_dat5 */
  61                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad6.mmc1_dat6 */
  62                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE1)        /* gpmc_ad7.mmc1_dat7 */
  63                 >;
  64         };
  65 };
  66
  67 &mmc2 {
  68         pinctrl-names = "default";
  69         pinctrl-0 = <&emmc_pins>;
  70         vmmc-supply = <&vmmc_reg>;
  71         bus-width = <8>;
  72         non-removable;
  73         status = "disabled";
  74 };
  75
  76 /* Ethernet */
  77 &am33xx_pinmux {
  78         ethernet0_pins: pinmux_ethernet0 {
  79                 pinctrl-single,pins = <
  80                         AM33XX_PADCONF(AM335X_PIN_MII1_CRS, PIN_INPUT_PULLDOWN, MUX_MODE1)
  81                         AM33XX_PADCONF(AM335X_PIN_MII1_RX_ER, PIN_INPUT_PULLDOWN, MUX_MODE1)
  82                         AM33XX_PADCONF(AM335X_PIN_MII1_TX_EN, PIN_OUTPUT, MUX_MODE1)
  83                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD1, PIN_OUTPUT, MUX_MODE1)
  84                         AM33XX_PADCONF(AM335X_PIN_MII1_TXD0, PIN_OUTPUT, MUX_MODE1)
  85                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD1, PIN_INPUT_PULLDOWN, MUX_MODE1)
  86                         AM33XX_PADCONF(AM335X_PIN_MII1_RXD0, PIN_INPUT_PULLDOWN, MUX_MODE1)
  87                         AM33XX_PADCONF(AM335X_PIN_RMII1_REF_CLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
  88                 >;
  89         };
  90
  91         mdio_pins: pinmux_mdio {
  92                 pinctrl-single,pins = <
  93                         /* MDIO */
  94                         AM33XX_PADCONF(AM335X_PIN_MDIO, PIN_INPUT_PULLUP | SLEWCTRL_FAST, MUX_MODE0)
  95                         AM33XX_PADCONF(AM335X_PIN_MDC, PIN_OUTPUT_PULLUP, MUX_MODE0)
  96                 >;
  97         };
  98 };
  99
 100 &cpsw_port1 {
 101         phy-handle = <&phy0>;
 102         phy-mode = "rmii";
 103         ti,dual-emac-pvid = <1>;
 104 };
 105
 106 &cpsw_port2 {
 107         status = "disabled";
 108 };
 109
 110 &davinci_mdio_sw {
 111         pinctrl-names = "default";
 112         pinctrl-0 = <&mdio_pins>;
 113
 114         phy0: ethernet-phy@0 {
 115                 reg = <0>;
 116         };
 117 };
 118
 119 &mac_sw {
 120         pinctrl-names = "default";
 121         pinctrl-0 = <&ethernet0_pins>;
 122         status = "okay";
 123 };
 124
 125 /* I2C Busses */
 126 &am33xx_pinmux {
 127         i2c0_pins: pinmux_i2c0 {
 128                 pinctrl-single,pins = <
 129                         AM33XX_PADCONF(AM335X_PIN_I2C0_SDA, PIN_INPUT, MUX_MODE0)
 130                         AM33XX_PADCONF(AM335X_PIN_I2C0_SCL, PIN_INPUT, MUX_MODE0)
 131                 >;
 132         };
 133 };
 134
 135 &i2c0 {
 136         pinctrl-names = "default";
 137         pinctrl-0 = <&i2c0_pins>;
 138         clock-frequency = <400000>;
 139         status = "okay";
 140
 141         tps: pmic@2d {
 142                 reg = <0x2d>;
 143         };
 144
 145         i2c_tmp102: temp@4b {
 146                 compatible = "ti,tmp102";
 147                 reg = <0x4b>;
 148                 status = "disabled";
 149         };
 150
 151         i2c_eeprom: eeprom@52 {
 152                 compatible = "atmel,24c32";
 153                 pagesize = <32>;
 154                 reg = <0x52>;
 155                 status = "disabled";
 156         };
 157
 158         i2c_rtc: rtc@68 {
 159                 compatible = "microcrystal,rv4162";
 160                 reg = <0x68>;
 161                 status = "disabled";
 162         };
 163 };
 164
 165 /* NAND memory */
 166 &am33xx_pinmux {
 167                 nandflash_pins: pinmux_nandflash {
 168                         pinctrl-single,pins = <
 169                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD0, PIN_INPUT_PULLUP, MUX_MODE0)
 170                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD1, PIN_INPUT_PULLUP, MUX_MODE0)
 171                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD2, PIN_INPUT_PULLUP, MUX_MODE0)
 172                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD3, PIN_INPUT_PULLUP, MUX_MODE0)
 173                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD4, PIN_INPUT_PULLUP, MUX_MODE0)
 174                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD5, PIN_INPUT_PULLUP, MUX_MODE0)
 175                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD6, PIN_INPUT_PULLUP, MUX_MODE0)
 176                         AM33XX_PADCONF(AM335X_PIN_GPMC_AD7, PIN_INPUT_PULLUP, MUX_MODE0)
 177                         AM33XX_PADCONF(AM335X_PIN_GPMC_WAIT0, PIN_INPUT_PULLUP, MUX_MODE0)
 178                         AM33XX_PADCONF(AM335X_PIN_GPMC_CSN0, PIN_OUTPUT, MUX_MODE0)
 179                         AM33XX_PADCONF(AM335X_PIN_GPMC_ADVN_ALE, PIN_OUTPUT, MUX_MODE0)
 180                         AM33XX_PADCONF(AM335X_PIN_GPMC_OEN_REN, PIN_OUTPUT, MUX_MODE0)
 181                         AM33XX_PADCONF(AM335X_PIN_GPMC_WEN, PIN_OUTPUT, MUX_MODE0)
 182                         AM33XX_PADCONF(AM335X_PIN_GPMC_BEN0_CLE, PIN_OUTPUT, MUX_MODE0)
 183                 >;
 184         };
 185 };
 186
 187 &elm {
 188         status = "okay";
 189 };
 190
 191 &gpmc {
 192         status = "disabled";
 193         pinctrl-names = "default";
 194         pinctrl-0 = <&nandflash_pins>;
 195         ranges = <0 0 0x08000000 0x1000000>;   /* CS0: NAND */
 196         nandflash: nand@0,0 {
 197                 compatible = "ti,omap2-nand";
 198                 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */
 199                 interrupt-parent = <&gpmc>;
 200                 interrupts = <0 IRQ_TYPE_NONE>, /* fifoevent */
 201                              <1 IRQ_TYPE_NONE>; /* termcount */
 202                 rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
 203                 nand-bus-width = <8>;
 204                 ti,nand-ecc-opt = "bch8";
 205                 gpmc,device-nand = "true";
 206                 gpmc,device-width = <1>;
 207                 gpmc,sync-clk-ps = <0>;
 208                 gpmc,cs-on-ns = <0>;
 209                 gpmc,cs-rd-off-ns = <30>;
 210                 gpmc,cs-wr-off-ns = <30>;
 211                 gpmc,adv-on-ns = <0>;
 212                 gpmc,adv-rd-off-ns = <30>;
 213                 gpmc,adv-wr-off-ns = <30>;
 214                 gpmc,we-on-ns = <0>;
 215                 gpmc,we-off-ns = <20>;
 216                 gpmc,oe-on-ns = <10>;
 217                 gpmc,oe-off-ns = <30>;
 218                 gpmc,access-ns = <30>;
 219                 gpmc,rd-cycle-ns = <30>;
 220                 gpmc,wr-cycle-ns = <30>;
 221                 gpmc,bus-turnaround-ns = <0>;
 222                 gpmc,cycle2cycle-delay-ns = <50>;
 223                 gpmc,cycle2cycle-diffcsen;
 224                 gpmc,clk-activation-ns = <0>;
 225                 gpmc,wr-access-ns = <30>;
 226                 gpmc,wr-data-mux-bus-ns = <0>;
 227
 228                 ti,elm-id = <&elm>;
 229
 230                 #address-cells = <1>;
 231                 #size-cells = <1>;
 232         };
 233 };
 234
 235 /* Power */
 236 #include "tps65910.dtsi"
 237
 238 &tps {
 239         vcc1-supply = <&vcc5v>;
 240         vcc2-supply = <&vcc5v>;
 241         vcc3-supply = <&vcc5v>;
 242         vcc4-supply = <&vcc5v>;
 243         vcc5-supply = <&vcc5v>;
 244         vcc6-supply = <&vcc5v>;
 245         vcc7-supply = <&vcc5v>;
 246         vccio-supply = <&vcc5v>;
 247
 248         regulators {
 249                 vrtc_reg: regulator@0 {
 250                         regulator-always-on;
 251                 };
 252
 253                 vio_reg: regulator@1 {
 254                         regulator-always-on;
 255                 };
 256
 257                 vdd1_reg: regulator@2 {
 258                         /* VDD_MPU voltage limits 0.95V - 1.325V with +/-4% tolerance */
 259                         regulator-name = "vdd_mpu";
 260                         regulator-min-microvolt = <912500>;
 261                         regulator-max-microvolt = <1378000>;
 262                         regulator-boot-on;
 263                         regulator-always-on;
 264                 };
 265
 266                 vdd2_reg: regulator@3 {
 267                         /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */
 268                         regulator-name = "vdd_core";
 269                         regulator-min-microvolt = <912500>;
 270                         regulator-max-microvolt = <1150000>;
 271                         regulator-boot-on;
 272                         regulator-always-on;
 273                 };
 274
 275                 vdd3_reg: regulator@4 {
 276                         regulator-always-on;
 277                 };
 278
 279                 vdig1_reg: regulator@5 {
 280                         regulator-name = "vdig1_1p8v";
 281                         regulator-min-microvolt = <1800000>;
 282                         regulator-max-microvolt = <1800000>;
 283                 };
 284
 285                 vdig2_reg: regulator@6 {
 286                         regulator-always-on;
 287                 };
 288
 289                 vpll_reg: regulator@7 {
 290                         regulator-always-on;
 291                 };
 292
 293                 vdac_reg: regulator@8 {
 294                         regulator-always-on;
 295                 };
 296
 297                 vaux1_reg: regulator@9 {
 298                         regulator-always-on;
 299                 };
 300
 301                 vaux2_reg: regulator@10 {
 302                         regulator-always-on;
 303                 };
 304
 305                 vaux33_reg: regulator@11 {
 306                         regulator-always-on;
 307                 };
 308
 309                 vmmc_reg: regulator@12 {
 310                         regulator-min-microvolt = <3300000>;
 311                         regulator-max-microvolt = <3300000>;
 312                         regulator-always-on;
 313                 };
 314         };
 315 };
 316
 317 /* SPI Busses */
 318 &am33xx_pinmux {
 319         spi0_pins: pinmux_spi0 {
 320                 pinctrl-single,pins = <
 321                         AM33XX_PADCONF(AM335X_PIN_SPI0_SCLK, PIN_INPUT_PULLDOWN, MUX_MODE0)
 322                         AM33XX_PADCONF(AM335X_PIN_SPI0_D0, PIN_INPUT_PULLDOWN, MUX_MODE0)
 323                         AM33XX_PADCONF(AM335X_PIN_SPI0_D1, PIN_INPUT_PULLUP, MUX_MODE0)
 324                         AM33XX_PADCONF(AM335X_PIN_SPI0_CS0, PIN_INPUT_PULLUP, MUX_MODE0)
 325                 >;
 326         };
 327 };
 328
 329 &spi0 {
 330         pinctrl-names = "default";
 331         pinctrl-0 = <&spi0_pins>;
 332         status = "okay";
 333
 334         serial_flash: m25p80@0 {
 335                 compatible = "jedec,spi-nor";
 336                 spi-max-frequency = <48000000>;
 337                 reg = <0x0>;
 338                 m25p,fast-read;
 339                 status = "disabled";
 340                 #address-cells = <1>;
 341                 #size-cells = <1>;
 342         };
 343 };