1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * TLB Exception Handling for ARC
5 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
7 * Vineetg: April 2011 :
8 * -MMU v1: moved out legacy code into a seperate file
9 * -MMU v3: PD{0,1} bits layout changed: They don't overlap anymore,
10 * helps avoid a shift when preparing PD0 from PTE
13 * -For MMU V2, we need not do heuristics at the time of commiting a D-TLB
14 * entry, so that it doesn't knock out it's I-TLB entry
15 * -Some more fine tuning:
16 * bmsk instead of add, asl.cc instead of branch, delay slot utilise etc
19 * -Practically rewrote the I/D TLB Miss handlers
20 * Now 40 and 135 instructions a peice as compared to 131 and 449 resp.
21 * Hence Leaner by 1.5 K
22 * Used Conditional arithmetic to replace excessive branching
23 * Also used short instructions wherever possible
25 * Vineetg: Aug 13th 2008
26 * -Passing ECR (Exception Cause REG) to do_page_fault( ) for printing
27 * more information in case of a Fatality
29 * Vineetg: March 25th Bug #92690
30 * -Added Debug Code to check if sw-ASID == hw-ASID
32 * Rahul Trivedi, Amit Bhor: Codito Technologies 2004
35 #include <linux/linkage.h>
36 #include <linux/pgtable.h>
37 #include <asm/entry.h>
39 #include <asm/arcregs.h>
40 #include <asm/cache.h>
41 #include <asm/processor.h>
43 #ifdef CONFIG_ISA_ARCOMPACT
44 ;-----------------------------------------------------------------
45 ; ARC700 Exception Handling doesn't auto-switch stack and it only provides
46 ; ONE scratch AUX reg "ARC_REG_SCRATCH_DATA0"
48 ; For Non-SMP, the scratch AUX reg is repurposed to cache task PGD, so a
49 ; "global" is used to free-up FIRST core reg to be able to code the rest of
50 ; exception prologue (IRQ auto-disabled on Exceptions, so it's IRQ-safe).
51 ; Since the Fast Path TLB Miss handler is coded with 4 regs, the remaining 3
52 ; need to be saved as well by extending the "global" to be 4 words. Hence
53 ; ".size ex_saved_reg1, 16"
54 ; [All of this dance is to avoid stack switching for each TLB Miss, since we
55 ; only need to save only a handful of regs, as opposed to complete reg file]
57 ; For ARC700 SMP, the "global" obviously can't be used for free up the FIRST
58 ; core reg as it will not be SMP safe.
59 ; Thus scratch AUX reg is used (and no longer used to cache task PGD).
60 ; To save the rest of 3 regs - per cpu, the global is made "per-cpu".
61 ; Epilogue thus has to locate the "per-cpu" storage for regs.
62 ; To avoid cache line bouncing the per-cpu global is aligned/sized per
63 ; L1_CACHE_SHIFT, despite fundamentally needing to be 12 bytes only. Hence
64 ; ".size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)"
66 ; As simple as that....
67 ;--------------------------------------------------------------------------
69 ; scratch memory to save [r0-r3] used to code TLB refill Handler
70 ARCFP_DATA ex_saved_reg1
71 .align 1 << L1_CACHE_SHIFT
72 .type ex_saved_reg1, @object
74 .size ex_saved_reg1, (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
76 .zero (CONFIG_NR_CPUS << L1_CACHE_SHIFT)
78 .size ex_saved_reg1, 16
83 .macro TLBMISS_FREEUP_REGS
85 sr r0, [ARC_REG_SCRATCH_DATA0] ; freeup r0 to code with
86 GET_CPU_ID r0 ; get to per cpu scratch mem,
87 asl r0, r0, L1_CACHE_SHIFT ; cache line wide per cpu
88 add r0, @ex_saved_reg1, r0
90 st r0, [@ex_saved_reg1]
91 mov_s r0, @ex_saved_reg1
98 .macro TLBMISS_RESTORE_REGS
100 GET_CPU_ID r0 ; get to per cpu scratch mem
101 asl r0, r0, L1_CACHE_SHIFT ; each is cache line wide
102 add r0, @ex_saved_reg1, r0
106 lr r0, [ARC_REG_SCRATCH_DATA0]
108 mov_s r0, @ex_saved_reg1
118 .macro TLBMISS_FREEUP_REGS
119 #ifdef CONFIG_ARC_HAS_LL64
130 .macro TLBMISS_RESTORE_REGS
131 #ifdef CONFIG_ARC_HAS_LL64
144 ;============================================================================
145 ;TLB Miss handling Code
146 ;============================================================================
148 ;-----------------------------------------------------------------------------
149 ; This macro does the page-table lookup for the faulting address.
150 ; OUT: r0 = PTE faulted on, r1 = ptr to PTE, r2 = Faulting V-address
151 .macro LOAD_FAULT_PTE
155 #ifdef CONFIG_ISA_ARCV2
156 lr r1, [ARC_REG_SCRATCH_DATA0] ; current pgd
158 GET_CURR_TASK_ON_CPU r1
159 ld r1, [r1, TASK_ACT_MM]
163 lsr r0, r2, PGDIR_SHIFT ; Bits for indexing into PGD
164 ld.as r3, [r1, r0] ; PGD entry corresp to faulting addr
166 bz do_slow_path_pf ; if no Page Table, do page fault
168 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
169 and.f 0, r3, _PAGE_HW_SZ ; Is this Huge PMD (thp)
171 bnz.d 2f ; YES: PGD == PMD has THP PTE: stop pgd walk
175 and r1, r3, PAGE_MASK
177 ; Get the PTE entry: The idea is
178 ; (1) x = addr >> PAGE_SHIFT -> masks page-off bits from @fault-addr
179 ; (2) y = x & (PTRS_PER_PTE - 1) -> to get index
180 ; (3) z = (pgtbl + y * 4)
182 #ifdef CONFIG_ARC_HAS_PAE40
183 #define PTE_SIZE_LOG 3 /* 8 == 2 ^ 3 */
185 #define PTE_SIZE_LOG 2 /* 4 == 2 ^ 2 */
188 ; multiply in step (3) above avoided by shifting lesser in step (1)
189 lsr r0, r2, ( PAGE_SHIFT - PTE_SIZE_LOG )
190 and r0, r0, ( (PTRS_PER_PTE - 1) << PTE_SIZE_LOG )
191 ld.aw r0, [r1, r0] ; r0: PTE (lower word only for PAE40)
198 ;-----------------------------------------------------------------
199 ; Convert Linux PTE entry into TLB entry
200 ; A one-word PTE entry is programmed as two-word TLB Entry [PD0:PD1] in mmu
201 ; (for PAE40, two-words PTE, while three-word TLB Entry [PD0:PD1:PD1HI])
202 ; IN: r0 = PTE, r1 = ptr to PTE
204 .macro CONV_PTE_TO_TLB
205 and r3, r0, PTE_BITS_RWX ; r w x
206 asl r2, r3, 3 ; Kr Kw Kx 0 0 0 (GLOBAL, kernel only)
207 and.f 0, r0, _PAGE_GLOBAL
208 or.z r2, r2, r3 ; Kr Kw Kx Ur Uw Ux (!GLOBAL, user page)
210 and r3, r0, PTE_BITS_NON_RWX_IN_PD1 ; Extract PFN+cache bits from PTE
213 sr r3, [ARC_REG_TLBPD1] ; paddr[31..13] | Kr Kw Kx Ur Uw Ux | C
214 #ifdef CONFIG_ARC_HAS_PAE40
215 ld r3, [r1, 4] ; paddr[39..32]
216 sr r3, [ARC_REG_TLBPD1HI]
219 and r2, r0, PTE_BITS_IN_PD0 ; Extract other PTE flags: (V)alid, (G)lb
221 lr r3,[ARC_REG_TLBPD0] ; MMU prepares PD0 with vaddr and asid
223 or r3, r3, r2 ; S | vaddr | {sasid|asid}
224 sr r3,[ARC_REG_TLBPD0] ; rewrite PD0
227 ;-----------------------------------------------------------------
228 ; Commit the TLB entry into MMU
230 .macro COMMIT_ENTRY_TO_MMU
231 #ifdef CONFIG_ARC_MMU_V3
233 /* Get free TLB slot: Set = computed from vaddr, way = random */
234 sr TLBGetIndex, [ARC_REG_TLBCOMMAND]
236 /* Commit the Write */
237 sr TLBWriteNI, [ARC_REG_TLBCOMMAND]
240 sr TLBInsertEntry, [ARC_REG_TLBCOMMAND]
247 ARCFP_CODE ;Fast Path Code, candidate for ICCM
249 ;-----------------------------------------------------------------------------
250 ; I-TLB Miss Exception Handler
251 ;-----------------------------------------------------------------------------
257 ;----------------------------------------------------------------
258 ; Get the PTE corresponding to V-addr accessed, r2 is setup with EFA
261 ;----------------------------------------------------------------
262 ; VERIFY_PTE: Check if PTE permissions approp for executing code
263 cmp_s r2, VMALLOC_START
264 mov_s r2, (_PAGE_PRESENT | _PAGE_EXECUTE)
265 or.hs r2, r2, _PAGE_GLOBAL
267 and r3, r0, r2 ; Mask out NON Flag bits from PTE
268 xor.f r3, r3, r2 ; check ( ( pte & flags_test ) == flags_test )
271 ; Let Linux VM know that the page was accessed
272 or r0, r0, _PAGE_ACCESSED ; set Accessed Bit
273 st_s r0, [r1] ; Write back PTE
278 EV_TLBMissI_fast_ret: ; additional label for VDK OS-kit instrumentation
283 ;-----------------------------------------------------------------------------
284 ; D-TLB Miss Exception Handler
285 ;-----------------------------------------------------------------------------
291 ;----------------------------------------------------------------
292 ; Get the PTE corresponding to V-addr accessed
293 ; If PTE exists, it will setup, r0 = PTE, r1 = Ptr to PTE, r2 = EFA
296 ;----------------------------------------------------------------
297 ; VERIFY_PTE: Chk if PTE permissions approp for data access (R/W/R+W)
299 cmp_s r2, VMALLOC_START
300 mov_s r2, _PAGE_PRESENT ; common bit for K/U PTE
301 or.hs r2, r2, _PAGE_GLOBAL ; kernel PTE only
303 ; Linux PTE [RWX] bits are semantically overloaded:
304 ; -If PAGE_GLOBAL set, they refer to kernel-only flags (vmalloc)
305 ; -Otherwise they are user-mode permissions, and those are exactly
306 ; same for kernel mode as well (e.g. copy_(to|from)_user)
309 btst_s r3, ECR_C_BIT_DTLB_LD_MISS ; Read Access
310 or.nz r2, r2, _PAGE_READ ; chk for Read flag in PTE
311 btst_s r3, ECR_C_BIT_DTLB_ST_MISS ; Write Access
312 or.nz r2, r2, _PAGE_WRITE ; chk for Write flag in PTE
313 ; Above laddering takes care of XCHG access (both R and W)
315 ; By now, r2 setup with all the Flags we need to check in PTE
316 and r3, r0, r2 ; Mask out NON Flag bits from PTE
317 brne.d r3, r2, do_slow_path_pf ; is ((pte & flags_test) == flags_test)
319 ;----------------------------------------------------------------
320 ; UPDATE_PTE: Let Linux VM know that page was accessed/dirty
321 or r0, r0, _PAGE_ACCESSED ; Accessed bit always
322 or.nz r0, r0, _PAGE_DIRTY ; if Write, set Dirty bit as well
323 st_s r0, [r1] ; Write back PTE
329 EV_TLBMissD_fast_ret: ; additional label for VDK OS-kit instrumentation
332 ;-------- Common routine to call Linux Page Fault Handler -----------
335 #ifdef CONFIG_ISA_ARCV2
336 ; Set Z flag if exception in U mode. Hardware micro-ops do this on any
337 ; taken interrupt/exception, and thus is already the case at the entry
338 ; above, but ensuing code would have already clobbered.
339 ; EXCEPTION_PROLOGUE called in slow path, relies on correct Z flag set
342 and r2, r2, STATUS_U_MASK
343 bxor.f 0, r2, STATUS_U_BIT
346 ; Restore the 4-scratch regs saved by fast path miss handler
349 ; Slow path TLB Miss handled as a regular ARC Exception
350 ; (stack switching / save the complete reg-file).