1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
6 * -Folded PAGE_PRESENT (used by VM) and PAGE_VALID (used by MMU) into 1.
7 * They are semantically the same although in different contexts
8 * VALID marks a TLB entry exists and it will only happen if PRESENT
9 * - Utilise some unused free bits to confine PTE flags to 12 bits
10 * This is a must for 4k pg-sz
12 * vineetg: Mar 2011 - changes to accommodate MMU TLB Page Descriptor mods
13 * -TLB Locking never really existed, except for initial specs
14 * -SILENT_xxx not needed for our port
15 * -Per my request, MMU V3 changes the layout of some of the bits
16 * to avoid a few shifts in TLB Miss handlers.
19 * -PGD entry no longer contains any flags. If empty it is 0, otherwise has
20 * Pg-Tbl ptr. Thus pmd_present(), pmd_valid(), pmd_set( ) become simpler
23 * -Switched form 8:11:13 split for page table lookup to 11:8:13
24 * -this speeds up page table allocation itself as we now have to memset 1K
25 * instead of 8k per page table.
26 * -TODO: Right now page table alloc is 8K and rest 7K is unused
29 * Amit Bhor, Sameer Dhavale: Codito Technologies 2004
32 #ifndef _ASM_ARC_PGTABLE_H
33 #define _ASM_ARC_PGTABLE_H
35 #include <linux/bits.h>
36 #include <asm-generic/pgtable-nopmd.h>
40 /**************************************************************************
43 * ARC700 MMU only deals with softare managed TLB entries.
44 * Page Tables are purely for Linux VM's consumption and the bits below are
45 * suited to that (uniqueness). Hence some are not implemented in the TLB and
46 * some have different value in TLB.
47 * e.g. MMU v2: K_READ bit is 8 and so is GLOBAL (possible because they live in
48 * seperate PD0 and PD1, which combined forms a translation entry)
49 * while for PTE perspective, they are 8 and 9 respectively
50 * with MMU v3: Most bits (except SHARED) represent the exact hardware pos
51 * (saves some bit shift ops in TLB Miss hdlrs)
54 #define _PAGE_CACHEABLE (1<<0) /* Page is cached (H) */
55 #define _PAGE_EXECUTE (1<<1) /* Page has user execute perm (H) */
56 #define _PAGE_WRITE (1<<2) /* Page has user write perm (H) */
57 #define _PAGE_READ (1<<3) /* Page has user read perm (H) */
58 #define _PAGE_ACCESSED (1<<4) /* Page is accessed (S) */
59 #define _PAGE_DIRTY (1<<5) /* Page modified (dirty) (S) */
60 #define _PAGE_SPECIAL (1<<6)
62 #define _PAGE_GLOBAL (1<<8) /* Page is global (H) */
63 #define _PAGE_PRESENT (1<<9) /* TLB entry is valid (H) */
65 #ifdef CONFIG_ARC_MMU_V4
66 #define _PAGE_HW_SZ (1<<10) /* Page Size indicator (H): 0 normal, 1 super */
69 #define _PAGE_SHARED_CODE (1<<11) /* Shared Code page with cmn vaddr
70 usable for shared TLB entries (H) */
71 /* vmalloc permissions */
72 #define _K_PAGE_PERMS (_PAGE_EXECUTE | _PAGE_WRITE | _PAGE_READ | \
73 _PAGE_GLOBAL | _PAGE_PRESENT)
75 #ifndef CONFIG_ARC_CACHE_PAGES
76 #undef _PAGE_CACHEABLE
77 #define _PAGE_CACHEABLE 0
84 /* Defaults for every user page */
85 #define ___DEF (_PAGE_PRESENT | _PAGE_CACHEABLE)
87 /* Set of bits not changed in pte_modify */
88 #define _PAGE_CHG_MASK (PAGE_MASK_PHYS | _PAGE_ACCESSED | _PAGE_DIRTY | \
90 /* More Abbrevaited helpers */
91 #define PAGE_U_NONE __pgprot(___DEF)
92 #define PAGE_U_R __pgprot(___DEF | _PAGE_READ)
93 #define PAGE_U_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE)
94 #define PAGE_U_X_R __pgprot(___DEF | _PAGE_READ | _PAGE_EXECUTE)
95 #define PAGE_U_X_W_R __pgprot(___DEF | _PAGE_READ | _PAGE_WRITE | \
98 #define PAGE_SHARED PAGE_U_W_R
100 /* While kernel runs out of unstranslated space, vmalloc/modules use a chunk of
101 * user vaddr space - visible in all addr spaces, but kernel mode only
102 * Thus Global, all-kernel-access, no-user-access, cached
104 #define PAGE_KERNEL __pgprot(_K_PAGE_PERMS | _PAGE_CACHEABLE)
106 /**************************************************************************
107 * Mapping of vm_flags (Generic VM) to PTE flags (arch specific)
109 * Certain cases have 1:1 mapping
110 * e.g. __P101 means VM_READ, VM_EXEC and !VM_SHARED
111 * which directly corresponds to PAGE_U_X_R
113 * Other rules which cause the divergence from 1:1 mapping
115 * 1. Although ARC700 can do exclusive execute/write protection (meaning R
116 * can be tracked independet of X/W unlike some other CPUs), still to
117 * keep things consistent with other archs:
118 * -Write implies Read: W => R
119 * -Execute implies Read: X => R
121 * 2. Pvt Writable doesn't have Write Enabled initially: Pvt-W => !W
122 * This is to enable COW mechanism
125 #define __P000 PAGE_U_NONE
126 #define __P001 PAGE_U_R
127 #define __P010 PAGE_U_R /* Pvt-W => !W */
128 #define __P011 PAGE_U_R /* Pvt-W => !W */
129 #define __P100 PAGE_U_X_R /* X => R */
130 #define __P101 PAGE_U_X_R
131 #define __P110 PAGE_U_X_R /* Pvt-W => !W and X => R */
132 #define __P111 PAGE_U_X_R /* Pvt-W => !W */
134 #define __S000 PAGE_U_NONE
135 #define __S001 PAGE_U_R
136 #define __S010 PAGE_U_W_R /* W => R */
137 #define __S011 PAGE_U_W_R
138 #define __S100 PAGE_U_X_R /* X => R */
139 #define __S101 PAGE_U_X_R
140 #define __S110 PAGE_U_X_W_R /* X => R */
141 #define __S111 PAGE_U_X_W_R
143 /****************************************************************
144 * 2 tier (PGD:PTE) software page walker
146 * [31] 32 bit virtual address [0]
147 * -------------------------------------------------------
148 * | | <------------ PGDIR_SHIFT ----------> |
150 * | BITS_FOR_PGD | BITS_FOR_PTE | <-- PAGE_SHIFT --> |
151 * -------------------------------------------------------
153 * | | --> off in page frame
154 * | ---> index into Page Table
155 * ----> index into Page Directory
157 * In a single page size configuration, only PAGE_SHIFT is fixed
158 * So both PGD and PTE sizing can be tweaked
159 * e.g. 8K page (PAGE_SHIFT 13) can have
160 * - PGDIR_SHIFT 21 -> 11:8:13 address split
161 * - PGDIR_SHIFT 24 -> 8:11:13 address split
163 * If Super Page is configured, PGDIR_SHIFT becomes fixed too,
164 * so the sizing flexibility is gone.
167 #if defined(CONFIG_ARC_HUGEPAGE_16M)
168 #define PGDIR_SHIFT 24
169 #elif defined(CONFIG_ARC_HUGEPAGE_2M)
170 #define PGDIR_SHIFT 21
173 * Only Normal page support so "hackable" (see comment above)
174 * Default value provides 11:8:13 (8K), 11:9:12 (4K)
176 #define PGDIR_SHIFT 21
179 #define BITS_FOR_PTE (PGDIR_SHIFT - PAGE_SHIFT)
180 #define BITS_FOR_PGD (32 - PGDIR_SHIFT)
182 #define PGDIR_SIZE BIT(PGDIR_SHIFT) /* vaddr span, not PDG sz */
183 #define PGDIR_MASK (~(PGDIR_SIZE-1))
185 #define PTRS_PER_PTE BIT(BITS_FOR_PTE)
186 #define PTRS_PER_PGD BIT(BITS_FOR_PGD)
189 * Number of entries a user land program use.
190 * TASK_SIZE is the maximum vaddr that can be used by a userland program.
192 #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
195 /****************************************************************
196 * Bucket load of VM Helpers
201 #define pte_ERROR(e) \
202 pr_crit("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
203 #define pgd_ERROR(e) \
204 pr_crit("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
206 /* the zero page used for uninitialized and anonymous pages */
207 extern char empty_zero_page[PAGE_SIZE];
208 #define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
210 #define set_pte(pteptr, pteval) ((*(pteptr)) = (pteval))
211 #define set_pmd(pmdptr, pmdval) (*(pmdptr) = pmdval)
213 /* find the page descriptor of the Page Tbl ref by PMD entry */
214 #define pmd_page(pmd) virt_to_page(pmd_val(pmd) & PAGE_MASK)
216 /* find the logical addr (phy for ARC) of the Page Tbl ref by PMD entry */
217 #define pmd_page_vaddr(pmd) (pmd_val(pmd) & PAGE_MASK)
219 #define pte_none(x) (!pte_val(x))
220 #define pte_present(x) (pte_val(x) & _PAGE_PRESENT)
221 #define pte_clear(mm, addr, ptep) set_pte_at(mm, addr, ptep, __pte(0))
223 #define pmd_none(x) (!pmd_val(x))
224 #define pmd_bad(x) ((pmd_val(x) & ~PAGE_MASK))
225 #define pmd_present(x) (pmd_val(x))
226 #define pmd_leaf(x) (pmd_val(x) & _PAGE_HW_SZ)
227 #define pmd_clear(xp) do { pmd_val(*(xp)) = 0; } while (0)
229 #define pte_page(pte) pfn_to_page(pte_pfn(pte))
230 #define mk_pte(page, prot) pfn_pte(page_to_pfn(page), prot)
231 #define pfn_pte(pfn, prot) __pte(__pfn_to_phys(pfn) | pgprot_val(prot))
233 /* Don't use virt_to_pfn for macros below: could cause truncations for PAE40*/
234 #define pte_pfn(pte) (pte_val(pte) >> PAGE_SHIFT)
236 /* Zoo of pte_xxx function */
237 #define pte_read(pte) (pte_val(pte) & _PAGE_READ)
238 #define pte_write(pte) (pte_val(pte) & _PAGE_WRITE)
239 #define pte_dirty(pte) (pte_val(pte) & _PAGE_DIRTY)
240 #define pte_young(pte) (pte_val(pte) & _PAGE_ACCESSED)
241 #define pte_special(pte) (pte_val(pte) & _PAGE_SPECIAL)
243 #define PTE_BIT_FUNC(fn, op) \
244 static inline pte_t pte_##fn(pte_t pte) { pte_val(pte) op; return pte; }
246 PTE_BIT_FUNC(mknotpresent, &= ~(_PAGE_PRESENT));
247 PTE_BIT_FUNC(wrprotect, &= ~(_PAGE_WRITE));
248 PTE_BIT_FUNC(mkwrite, |= (_PAGE_WRITE));
249 PTE_BIT_FUNC(mkclean, &= ~(_PAGE_DIRTY));
250 PTE_BIT_FUNC(mkdirty, |= (_PAGE_DIRTY));
251 PTE_BIT_FUNC(mkold, &= ~(_PAGE_ACCESSED));
252 PTE_BIT_FUNC(mkyoung, |= (_PAGE_ACCESSED));
253 PTE_BIT_FUNC(exprotect, &= ~(_PAGE_EXECUTE));
254 PTE_BIT_FUNC(mkexec, |= (_PAGE_EXECUTE));
255 PTE_BIT_FUNC(mkspecial, |= (_PAGE_SPECIAL));
256 PTE_BIT_FUNC(mkhuge, |= (_PAGE_HW_SZ));
258 static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
260 return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
263 /* Macro to mark a page protection as uncacheable */
264 #define pgprot_noncached(prot) (__pgprot(pgprot_val(prot) & ~_PAGE_CACHEABLE))
266 static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
267 pte_t *ptep, pte_t pteval)
269 set_pte(ptep, pteval);
272 extern pgd_t swapper_pg_dir[] __aligned(PAGE_SIZE);
273 void update_mmu_cache(struct vm_area_struct *vma, unsigned long address,
276 /* Encode swap {type,off} tuple into PTE
277 * We reserve 13 bits for 5-bit @type, keeping bits 12-5 zero, ensuring that
278 * PAGE_PRESENT is zero in a PTE holding swap "identifier"
280 #define __swp_entry(type, off) ((swp_entry_t) { \
281 ((type) & 0x1f) | ((off) << 13) })
283 /* Decode a PTE containing swap "identifier "into constituents */
284 #define __swp_type(pte_lookalike) (((pte_lookalike).val) & 0x1f)
285 #define __swp_offset(pte_lookalike) ((pte_lookalike).val >> 13)
287 /* NOPs, to keep generic kernel happy */
288 #define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
289 #define __swp_entry_to_pte(x) ((pte_t) { (x).val })
291 #define kern_addr_valid(addr) (1)
293 #define pmd_pgtable(pmd) ((pgtable_t) pmd_page_vaddr(pmd))
296 * remap a physical page `pfn' of size `size' with page protection `prot'
297 * into virtual address `from'
299 #ifdef CONFIG_TRANSPARENT_HUGEPAGE
300 #include <asm/hugepage.h>
303 /* to cope with aliasing VIPT cache */
304 #define HAVE_ARCH_UNMAPPED_AREA
306 #endif /* __ASSEMBLY__ */