1 /* SPDX-License-Identifier: GPL-2.0-only */
3 * Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
10 #include <linux/threads.h> /* NR_CPUS */
13 /* MMU Management regs */
14 #define ARC_REG_MMU_BCR 0x06f
16 #ifdef CONFIG_ARC_MMU_V3
17 #define ARC_REG_TLBPD0 0x405
18 #define ARC_REG_TLBPD1 0x406
19 #define ARC_REG_TLBPD1HI 0 /* Dummy: allows code sharing with ARC700 */
20 #define ARC_REG_TLBINDEX 0x407
21 #define ARC_REG_TLBCOMMAND 0x408
22 #define ARC_REG_PID 0x409
23 #define ARC_REG_SCRATCH_DATA0 0x418
25 #define ARC_REG_TLBPD0 0x460
26 #define ARC_REG_TLBPD1 0x461
27 #define ARC_REG_TLBPD1HI 0x463
28 #define ARC_REG_TLBINDEX 0x464
29 #define ARC_REG_TLBCOMMAND 0x465
30 #define ARC_REG_PID 0x468
31 #define ARC_REG_SCRATCH_DATA0 0x46c
34 #if defined(CONFIG_ISA_ARCV2) || !defined(CONFIG_SMP)
35 #define ARC_USE_SCRATCH_REG
38 /* Bits in MMU PID register */
39 #define __TLB_ENABLE (1 << 31)
40 #define __PROG_ENABLE (1 << 30)
41 #define MMU_ENABLE (__TLB_ENABLE | __PROG_ENABLE)
43 /* Error code if probe fails */
44 #define TLB_LKUP_ERR 0x80000000
46 #ifdef CONFIG_ARC_MMU_V3
47 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x00000001)
49 #define TLB_DUP_ERR (TLB_LKUP_ERR | 0x40000000)
55 #define TLBGetIndex 0x3
57 #define TLBWriteNI 0x5 /* write JTLB without inv uTLBs */
58 #define TLBIVUTLB 0x6 /* explicitly inv uTLBs */
60 #ifdef CONFIG_ARC_MMU_V4
61 #define TLBInsertEntry 0x7
62 #define TLBDeleteEntry 0x8
68 unsigned long asid[NR_CPUS]; /* 8 bit MMU PID + Generation cycle */
71 #ifdef CONFIG_ARC_DBG_TLB_PARANOIA
72 void tlb_paranoid_check(unsigned int mm_asid, unsigned long address);
74 #define tlb_paranoid_check(a, b)
77 void arc_mmu_init(void);
78 extern char *arc_mmu_mumbojumbo(int cpu_id, char *buf, int len);
79 void read_decode_mmu_bcr(void);
81 static inline int is_pae40_enabled(void)
83 return IS_ENABLED(CONFIG_ARC_HAS_PAE40);
86 extern int pae40_exist_but_not_enab(void);
88 #endif /* !__ASSEMBLY__ */