1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * ARCv2 supports 64-bit exclusive load (LLOCKD) / store (SCONDD)
5 * - The address HAS to be 64-bit aligned
8 #ifndef _ASM_ARC_ATOMIC64_ARCV2_H
9 #define _ASM_ARC_ATOMIC64_ARCV2_H
12 s64 __aligned(8) counter;
15 #define ATOMIC64_INIT(a) { (a) }
17 static inline s64 arch_atomic64_read(const atomic64_t *v)
29 static inline void arch_atomic64_set(atomic64_t *v, s64 a)
32 * This could have been a simple assignment in "C" but would need
33 * explicit volatile. Otherwise gcc optimizers could elide the store
34 * which borked atomic64 self-test
35 * In the inline asm version, memory clobber needed for exact same
36 * reason, to tell gcc about the store.
38 * This however is not needed for sibling atomic64_add() etc since both
39 * load/store are explicitly done in inline asm. As long as API is used
40 * for each access, gcc has no way to optimize away any load/store
45 : "r"(a), "r"(&v->counter)
49 #define ATOMIC64_OP(op, op1, op2) \
50 static inline void arch_atomic64_##op(s64 a, atomic64_t *v) \
54 __asm__ __volatile__( \
56 " llockd %0, [%1] \n" \
57 " " #op1 " %L0, %L0, %L2 \n" \
58 " " #op2 " %H0, %H0, %H2 \n" \
59 " scondd %0, [%1] \n" \
62 : "r"(&v->counter), "ir"(a) \
66 #define ATOMIC64_OP_RETURN(op, op1, op2) \
67 static inline s64 arch_atomic64_##op##_return(s64 a, atomic64_t *v) \
73 __asm__ __volatile__( \
75 " llockd %0, [%1] \n" \
76 " " #op1 " %L0, %L0, %L2 \n" \
77 " " #op2 " %H0, %H0, %H2 \n" \
78 " scondd %0, [%1] \n" \
81 : "r"(&v->counter), "ir"(a) \
82 : "cc"); /* memory clobber comes from smp_mb() */ \
89 #define ATOMIC64_FETCH_OP(op, op1, op2) \
90 static inline s64 arch_atomic64_fetch_##op(s64 a, atomic64_t *v) \
96 __asm__ __volatile__( \
98 " llockd %0, [%2] \n" \
99 " " #op1 " %L1, %L0, %L3 \n" \
100 " " #op2 " %H1, %H0, %H3 \n" \
101 " scondd %1, [%2] \n" \
103 : "=&r"(orig), "=&r"(val) \
104 : "r"(&v->counter), "ir"(a) \
105 : "cc"); /* memory clobber comes from smp_mb() */ \
112 #define ATOMIC64_OPS(op, op1, op2) \
113 ATOMIC64_OP(op, op1, op2) \
114 ATOMIC64_OP_RETURN(op, op1, op2) \
115 ATOMIC64_FETCH_OP(op, op1, op2)
117 ATOMIC64_OPS(add, add.f, adc)
118 ATOMIC64_OPS(sub, sub.f, sbc)
119 ATOMIC64_OPS(and, and, and)
120 ATOMIC64_OPS(andnot, bic, bic)
121 ATOMIC64_OPS(or, or, or)
122 ATOMIC64_OPS(xor, xor, xor)
124 #define arch_atomic64_andnot arch_atomic64_andnot
125 #define arch_atomic64_fetch_andnot arch_atomic64_fetch_andnot
128 #undef ATOMIC64_FETCH_OP
129 #undef ATOMIC64_OP_RETURN
133 arch_atomic64_cmpxchg(atomic64_t *ptr, s64 expected, s64 new)
139 __asm__ __volatile__(
140 "1: llockd %0, [%1] \n"
141 " brne %L0, %L2, 2f \n"
142 " brne %H0, %H2, 2f \n"
143 " scondd %3, [%1] \n"
147 : "r"(ptr), "ir"(expected), "r"(new)
148 : "cc"); /* memory clobber comes from smp_mb() */
155 static inline s64 arch_atomic64_xchg(atomic64_t *ptr, s64 new)
161 __asm__ __volatile__(
162 "1: llockd %0, [%1] \n"
163 " scondd %2, [%1] \n"
168 : "cc"); /* memory clobber comes from smp_mb() */
176 * arch_atomic64_dec_if_positive - decrement by 1 if old value positive
177 * @v: pointer of type atomic64_t
179 * The function returns the old value of *v minus 1, even if
180 * the atomic variable, v, was not decremented.
183 static inline s64 arch_atomic64_dec_if_positive(atomic64_t *v)
189 __asm__ __volatile__(
190 "1: llockd %0, [%1] \n"
191 " sub.f %L0, %L0, 1 # w0 - 1, set C on borrow\n"
192 " sub.c %H0, %H0, 1 # if C set, w1 - 1\n"
193 " brlt %H0, 0, 2f \n"
194 " scondd %0, [%1] \n"
199 : "cc"); /* memory clobber comes from smp_mb() */
205 #define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive
208 * arch_atomic64_fetch_add_unless - add unless the number is a given value
209 * @v: pointer of type atomic64_t
210 * @a: the amount to add to v...
211 * @u: ...unless v is equal to u.
213 * Atomically adds @a to @v, if it was not @u.
214 * Returns the old value of @v
216 static inline s64 arch_atomic64_fetch_add_unless(atomic64_t *v, s64 a, s64 u)
222 __asm__ __volatile__(
223 "1: llockd %0, [%2] \n"
224 " brne %L0, %L4, 2f # continue to add since v != u \n"
225 " breq.d %H0, %H4, 3f # return since v == u \n"
227 " add.f %L1, %L0, %L3 \n"
228 " adc %H1, %H0, %H3 \n"
229 " scondd %1, [%2] \n"
232 : "=&r"(old), "=&r" (temp)
233 : "r"(&v->counter), "r"(a), "r"(u)
234 : "cc"); /* memory clobber comes from smp_mb() */
240 #define arch_atomic64_fetch_add_unless arch_atomic64_fetch_add_unless