1 # SPDX-License-Identifier: GPL-2.0-only
3 # Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
9 select ARCH_HAS_CACHE_LINE_SIZE
10 select ARCH_HAS_DEBUG_VM_PGTABLE
11 select ARCH_HAS_DMA_PREP_COHERENT
12 select ARCH_HAS_PTE_SPECIAL
13 select ARCH_HAS_SETUP_DMA_OPS
14 select ARCH_HAS_SYNC_DMA_FOR_CPU
15 select ARCH_HAS_SYNC_DMA_FOR_DEVICE
16 select ARCH_SUPPORTS_ATOMIC_RMW if ARC_HAS_LLSC
17 select ARCH_32BIT_OFF_T
18 select BUILDTIME_TABLE_SORT
19 select CLONE_BACKWARDS
21 select DMA_DIRECT_REMAP
22 select GENERIC_ATOMIC64 if !ISA_ARCV2 || !(ARC_HAS_LL64 && ARC_HAS_LLSC)
23 select GENERIC_FIND_FIRST_BIT
24 # for now, we don't need GENERIC_IRQ_PROBE, CONFIG_GENERIC_IRQ_CHIP
25 select GENERIC_IRQ_SHOW
26 select GENERIC_PCI_IOMAP
27 select GENERIC_PENDING_IRQ if SMP
28 select GENERIC_SCHED_CLOCK
29 select GENERIC_SMP_IDLE_THREAD
31 select HAVE_ARCH_TRACEHOOK
32 select HAVE_ARCH_TRANSPARENT_HUGEPAGE if ARC_MMU_V4
33 select HAVE_DEBUG_STACKOVERFLOW
34 select HAVE_DEBUG_KMEMLEAK
35 select HAVE_FUTEX_CMPXCHG if FUTEX
36 select HAVE_IOREMAP_PROT
37 select HAVE_KERNEL_GZIP
38 select HAVE_KERNEL_LZMA
40 select HAVE_KRETPROBES
41 select HAVE_MOD_ARCH_SPECIFIC
42 select HAVE_PERF_EVENTS
43 select HANDLE_DOMAIN_IRQ
45 select MODULES_USE_ELF_RELA
47 select OF_EARLY_FLATTREE
48 select PCI_SYSCALL if PCI
49 select PERF_USE_VMALLOC if ARC_CACHE_VIPT_ALIASING
50 select HAVE_ARCH_JUMP_LABEL if ISA_ARCV2 && !CPU_ENDIAN_BE32
53 config TRACE_IRQFLAGS_SUPPORT
56 config LOCKDEP_SUPPORT
59 config SCHED_OMIT_FRAME_POINTER
65 config ARCH_FLATMEM_ENABLE
74 config GENERIC_CALIBRATE_DELAY
77 config GENERIC_HWEIGHT
80 config STACKTRACE_SUPPORT
84 menu "ARC Architecture Configuration"
86 menu "ARC Platform/SoC/Board"
88 source "arch/arc/plat-tb10x/Kconfig"
89 source "arch/arc/plat-axs10x/Kconfig"
90 source "arch/arc/plat-hsdk/Kconfig"
95 prompt "ARC Instruction Set"
100 select CPU_NO_EFFICIENT_FFS
102 The original ARC ISA of ARC600/700 cores
106 select ARC_TIMERS_64BIT
108 ISA for the Next Generation ARC-HS cores
112 menu "ARC CPU Configuration"
116 default ARC_CPU_770 if ISA_ARCOMPACT
117 default ARC_CPU_HS if ISA_ARCV2
121 depends on ISA_ARCOMPACT
124 Support for ARC770 core introduced with Rel 4.10 (Summer 2011)
125 This core has a bunch of cool new features:
126 -MMU-v3: Variable Page Sz (4k, 8k, 16k), bigger J-TLB (128x4)
127 Shared Address Spaces (for sharing TLB entries in MMU)
128 -Caches: New Prog Model, Region Flush
129 -Insns: endian swap, load-locked/store-conditional, time-stamp-ctr
135 Support for ARC HS38x Cores based on ARCv2 ISA
136 The notable features are:
137 - SMP configurations of up to 4 cores with coherency
138 - Optional L2 Cache and IO-Coherency
139 - Revised Interrupt Architecture (multiple priorites, reg banks,
140 auto stack switch, auto regfile save/restore)
141 - MMUv4 (PIPT dcache, Huge Pages)
143 * 64bit load/store: LDD, STD
144 * Hardware assisted divide/remainder: DIV, REM
145 * Function prologue/epilogue: ENTER_S, LEAVE_S
146 * IRQ enable/disable: CLRI, SETI
147 * pop count: FFS, FLS
148 * SETcc, BMSKN, XBFU...
153 string "Override default -mcpu compiler flag"
156 Override default -mcpu=xxx compiler flag (which is set depending on
157 the ISA version) with the specified value.
158 NOTE: If specified flag isn't supported by current compiler the
159 ISA default value will be used as a fallback.
161 config CPU_BIG_ENDIAN
162 bool "Enable Big Endian Mode"
164 Build kernel for Big Endian Mode of ARC CPU
167 bool "Symmetric Multi-Processing"
168 select ARC_MCIP if ISA_ARCV2
170 This enables support for systems with more than one CPU.
175 int "Maximum number of CPUs (2-4096)"
179 config ARC_SMP_HALT_ON_RESET
180 bool "Enable Halt-on-reset boot mode"
182 In SMP configuration cores can be configured as Halt-on-reset
183 or they could all start at same time. For Halt-on-reset, non
184 masters are parked until Master kicks them so they can start off
185 at designated entry point. For other case, all jump to common
186 entry point and spin wait for Master's signal.
191 bool "ARConnect Multicore IP (MCIP) Support "
195 This IP block enables SMP in ARC-HS38 cores.
196 It provides for cross-core interrupts, multi-core debug
197 hardware semaphores, shared memory,....
200 bool "Enable Cache Support"
205 config ARC_CACHE_LINE_SHIFT
206 int "Cache Line Length (as power of 2)"
210 Starting with ARC700 4.9, Cache line length is configurable,
211 This option specifies "N", with Line-len = 2 power N
212 So line lengths of 32, 64, 128 are specified by 5,6,7, respectively
213 Linux only supports same line lengths for I and D caches.
215 config ARC_HAS_ICACHE
216 bool "Use Instruction Cache"
219 config ARC_HAS_DCACHE
220 bool "Use Data Cache"
223 config ARC_CACHE_PAGES
224 bool "Per Page Cache Control"
226 depends on ARC_HAS_ICACHE || ARC_HAS_DCACHE
228 This can be used to over-ride the global I/D Cache Enable on a
229 per-page basis (but only for pages accessed via MMU such as
230 Kernel Virtual address or User Virtual Address)
231 TLB entries have a per-page Cache Enable Bit.
232 Note that Global I/D ENABLE + Per Page DISABLE works but corollary
233 Global DISABLE + Per Page ENABLE won't work
235 config ARC_CACHE_VIPT_ALIASING
236 bool "Support VIPT Aliasing D$"
237 depends on ARC_HAS_DCACHE && ISA_ARCOMPACT
244 Single Cycle RAMS to store Fast Path Code
247 int "ICCM Size in KB"
249 depends on ARC_HAS_ICCM
254 Single Cycle RAMS to store Fast Path Data
257 int "DCCM Size in KB"
259 depends on ARC_HAS_DCCM
262 hex "DCCM map address"
264 depends on ARC_HAS_DCCM
268 default ARC_MMU_V3 if ARC_CPU_770
269 default ARC_MMU_V4 if ARC_CPU_HS
281 Fixed the deficiency of v1 - possible thrashing in memcpy scenario
282 when 2 D-TLB and 1 I-TLB entries index into same 2way set.
286 depends on ARC_CPU_770
288 Introduced with ARC700 4.10: New Features
289 Variable Page size (1k-16k), var JTLB size 128 x (2 or 4)
290 Shared Address Spaces (SASID)
302 prompt "MMU Page Size"
303 default ARC_PAGE_SIZE_8K
305 config ARC_PAGE_SIZE_8K
308 Choose between 8k vs 16k
310 config ARC_PAGE_SIZE_16K
312 depends on ARC_MMU_V3 || ARC_MMU_V4
314 config ARC_PAGE_SIZE_4K
316 depends on ARC_MMU_V3 || ARC_MMU_V4
321 prompt "MMU Super Page Size"
322 depends on ISA_ARCV2 && TRANSPARENT_HUGEPAGE
323 default ARC_HUGEPAGE_2M
325 config ARC_HUGEPAGE_2M
328 config ARC_HUGEPAGE_16M
333 config ARC_COMPACT_IRQ_LEVELS
334 depends on ISA_ARCOMPACT
335 bool "Setup Timer IRQ as high Priority"
336 # if SMP, LV2 enabled ONLY if ARC implementation has LV2 re-entrancy
339 config ARC_FPU_SAVE_RESTORE
340 bool "Enable FPU state persistence across context switch"
342 ARCompact FPU has internal registers to assist with Double precision
343 Floating Point operations. There are control and stauts registers
344 for floating point exceptions and rounding modes. These are
345 preserved across task context switch when enabled.
351 bool "Insn: LLOCK/SCOND (efficient atomic ops)"
353 depends on !ARC_CANT_LLSC
356 bool "Insn: SWAPE (endian-swap)"
361 config ARC_USE_UNALIGNED_MEM_ACCESS
362 bool "Enable unaligned access in HW"
364 select HAVE_EFFICIENT_UNALIGNED_ACCESS
366 The ARC HS architecture supports unaligned memory access
367 which is disabled by default. Enable unaligned access in
368 hardware and use software to use it
371 bool "Insn: 64bit LDD/STD"
373 Enable gcc to generate 64-bit load/store instructions
374 ISA mandates even/odd registers to allow encoding of two
375 dest operands with 2 possible source operands.
378 config ARC_HAS_DIV_REM
379 bool "Insn: div, divu, rem, remu"
382 config ARC_HAS_ACCL_REGS
383 bool "Reg Pair ACCL:ACCH (FPU and/or MPY > 6 and/or DSP)"
386 Depending on the configuration, CPU can contain accumulator reg-pair
387 (also referred to as r58:r59). These can also be used by gcc as GPR so
388 kernel needs to save/restore per process
390 config ARC_DSP_HANDLED
393 config ARC_DSP_SAVE_RESTORE_REGS
400 Depending on the configuration, CPU can contain DSP registers
401 (ACC0_GLO, ACC0_GHI, DSP_BFLY0, DSP_CTRL, DSP_FFT_CTRL).
402 Below are options describing how to handle these registers in
403 interrupt entry / exit and in context switch.
406 bool "No DSP extension presence in HW"
408 No DSP extension presence in HW
410 config ARC_DSP_KERNEL
411 bool "DSP extension in HW, no support for userspace"
412 select ARC_HAS_ACCL_REGS
413 select ARC_DSP_HANDLED
415 DSP extension presence in HW, no support for DSP-enabled userspace
416 applications. We don't save / restore DSP registers and only do
417 some minimal preparations so userspace won't be able to break kernel
419 config ARC_DSP_USERSPACE
420 bool "Support DSP for userspace apps"
421 select ARC_HAS_ACCL_REGS
422 select ARC_DSP_HANDLED
423 select ARC_DSP_SAVE_RESTORE_REGS
425 DSP extension presence in HW, support save / restore DSP registers to
426 run DSP-enabled userspace applications
428 config ARC_DSP_AGU_USERSPACE
429 bool "Support DSP with AGU for userspace apps"
430 select ARC_HAS_ACCL_REGS
431 select ARC_DSP_HANDLED
432 select ARC_DSP_SAVE_RESTORE_REGS
434 DSP and AGU extensions presence in HW, support save / restore DSP
435 and AGU registers to run DSP-enabled userspace applications
438 config ARC_IRQ_NO_AUTOSAVE
439 bool "Disable hardware autosave regfile on interrupts"
442 On HS cores, taken interrupt auto saves the regfile on stack.
443 This is programmable and can be optionally disabled in which case
444 software INTERRUPT_PROLOGUE/EPILGUE do the needed work
446 config ARC_LPB_DISABLE
447 bool "Disable loop buffer (LPB)"
449 On HS cores, loop buffer (LPB) is programmable in runtime and can
450 be optionally disabled.
454 endmenu # "ARC CPU Configuration"
456 config LINUX_LINK_BASE
457 hex "Kernel link address"
460 ARC700 divides the 32 bit phy address space into two equal halves
461 -Lower 2G (0 - 0x7FFF_FFFF ) is user virtual, translated by MMU
462 -Upper 2G (0x8000_0000 onwards) is untranslated, for kernel
463 Typically Linux kernel is linked at the start of untransalted addr,
464 hence the default value of 0x8zs.
465 However some customers have peripherals mapped at this addr, so
466 Linux needs to be scooted a bit.
467 If you don't know what the above means, leave this setting alone.
468 This needs to match memory start address specified in Device Tree
470 config LINUX_RAM_BASE
471 hex "RAM base address"
472 default LINUX_LINK_BASE
474 By default Linux is linked at base of RAM. However in some special
475 cases (such as HSDK), Linux can't be linked at start of DDR, hence
479 bool "High Memory Support"
480 select HAVE_ARCH_PFN_VALID
483 With ARC 2G:2G address split, only upper 2G is directly addressable by
484 kernel. Enable this to potentially allow access to rest of 2G and PAE
488 bool "Support for the 40-bit Physical Address Extension"
491 select PHYS_ADDR_T_64BIT
493 Enable access to physical memory beyond 4G, only supported on
494 ARC cores with 40 bit Physical Addressing support
496 config ARC_KVADDR_SIZE
497 int "Kernel Virtual Address Space size (MB)"
501 The kernel address space is carved out of 256MB of translated address
502 space for catering to vmalloc, modules, pkmap, fixmap. This however may
503 not suffice vmalloc requirements of a 4K CPU EZChip system. So allow
504 this to be stretched to 512 MB (by extending into the reserved
507 config ARC_CURR_IN_REG
508 bool "Dedicate Register r25 for current_task pointer"
511 This reserved Register R25 to point to Current Task in
512 kernel mode. This saves memory access for each such access
515 config ARC_EMUL_UNALIGNED
516 bool "Emulate unaligned memory access (userspace only)"
517 select SYSCTL_ARCH_UNALIGN_NO_WARN
518 select SYSCTL_ARCH_UNALIGN_ALLOW
519 depends on ISA_ARCOMPACT
521 This enables misaligned 16 & 32 bit memory access from user space.
522 Use ONLY-IF-ABS-NECESSARY as it will be very slow and also can hide
523 potential bugs in code
526 int "Timer Frequency"
529 config ARC_METAWARE_HLINK
530 bool "Support for Metaware debugger assisted Host access"
532 This options allows a Linux userland apps to directly access
533 host file system (open/creat/read/write etc) with help from
534 Metaware Debugger. This can come in handy for Linux-host communication
535 when there is no real usable peripheral such as EMAC.
543 config ARC_DW2_UNWIND
544 bool "Enable DWARF specific kernel stack unwind"
548 Compiles the kernel with DWARF unwind information and can be used
549 to get stack backtraces.
551 If you say Y here the resulting kernel image will be slightly larger
552 but not slower, and it will give very useful debugging information.
553 If you don't debug the kernel, you can say N, but we may not be able
554 to solve problems without frame unwind information
556 config ARC_DBG_TLB_PARANOIA
557 bool "Paranoia Checks in Low Level TLB Handlers"
559 config ARC_DBG_JUMP_LABEL
560 bool "Paranoid checks in Static Keys (jump labels) code"
561 depends on JUMP_LABEL
562 default y if STATIC_KEYS_SELFTEST
564 Enable paranoid checks and self-test of both ARC-specific and generic
565 part of static keys (jump labels) related code.
568 config ARC_BUILTIN_DTB_NAME
569 string "Built in DTB"
571 Set the name of the DTB to embed in the vmlinux binary
572 Leaving it blank selects the minimal "skeleton" dtb
574 endmenu # "ARC Architecture Configuration"
576 config FORCE_MAX_ZONEORDER
577 int "Maximum zone order"
578 default "12" if ARC_HUGEPAGE_16M
581 source "kernel/power/Kconfig"