Documentation/driver-api/media/drivers/ccs/ccs-regs.asc

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-3-Clause
   2 # Copyright (C) 2019--2020 Intel Corporation
   3
   4 # register                              rflags
   5 # - f   field   LSB     MSB             rflags
   6 # - e   enum    value                   # after a field
   7 # - e   enum    value   [LSB    MSB]
   8 # - b   bool    bit
   9 # - l   arg     name    min     max     elsize  [discontig...]
  10 #
  11 # rflags
  12 #       8, 16, 32       register bits (default is 8)
  13 #       v1.1            defined in version 1.1
  14 #       f               formula
  15 #       float_ireal     iReal or IEEE 754; 32 bits
  16 #       ireal           unsigned iReal
  17
  18 # general status registers
  19 module_model_id                         0x0000  16
  20 module_revision_number_major            0x0002  8
  21 frame_count                             0x0005  8
  22 pixel_order                             0x0006  8
  23 - e     GRBG                            0
  24 - e     RGGB                            1
  25 - e     BGGR                            2
  26 - e     GBRG                            3
  27 MIPI_CCS_version                        0x0007  8
  28 - e     v1_0                            0x10
  29 - e     v1_1                            0x11
  30 - f     major                           4       7
  31 - f     minor                           0       3
  32 data_pedestal                           0x0008  16
  33 module_manufacturer_id                  0x000e  16
  34 module_revision_number_minor            0x0010  8
  35 module_date_year                        0x0012  8
  36 module_date_month                       0x0013  8
  37 module_date_day                         0x0014  8
  38 module_date_phase                       0x0015  8
  39 - f                                     0       2
  40 - e     ts                              0
  41 - e     es                              1
  42 - e     cs                              2
  43 - e     mp                              3
  44 sensor_model_id                         0x0016  16
  45 sensor_revision_number                  0x0018  8
  46 sensor_firmware_version                 0x001a  8
  47 serial_number                           0x001c  32
  48 sensor_manufacturer_id                  0x0020  16
  49 sensor_revision_number_16               0x0022  16
  50
  51 # frame format description registers
  52 frame_format_model_type                 0x0040  8
  53 - e     2-byte                          1
  54 - e     4-byte                          2
  55 frame_format_model_subtype              0x0041  8
  56 - f     rows                            0       3
  57 - f     columns                         4       7
  58 frame_format_descriptor(n)              0x0042  16      f
  59 - l     n                               0       14      2
  60 - f     pixels                          0       11
  61 - f     pcode                           12      15
  62 - e     embedded                        1
  63 - e     dummy_pixel                     2
  64 - e     black_pixel                     3
  65 - e     dark_pixel                      4
  66 - e     visible_pixel                   5
  67 - e     manuf_specific_0                8
  68 - e     manuf_specific_1                9
  69 - e     manuf_specific_2                10
  70 - e     manuf_specific_3                11
  71 - e     manuf_specific_4                12
  72 - e     manuf_specific_5                13
  73 - e     manuf_specific_6                14
  74 frame_format_descriptor_4(n)            0x0060  32      f
  75 - l     n                               0       7       4
  76 - f     pixels                          0       15
  77 - f     pcode                           28      31
  78 - e     embedded                        1
  79 - e     dummy_pixel                     2
  80 - e     black_pixel                     3
  81 - e     dark_pixel                      4
  82 - e     visible_pixel                   5
  83 - e     manuf_specific_0                8
  84 - e     manuf_specific_1                9
  85 - e     manuf_specific_2                10
  86 - e     manuf_specific_3                11
  87 - e     manuf_specific_4                12
  88 - e     manuf_specific_5                13
  89 - e     manuf_specific_6                14
  90
  91 # analog gain description registers
  92 analog_gain_capability                  0x0080  16
  93 - e     global                          0
  94 - e     alternate_global                2
  95 analog_gain_code_min                    0x0084  16
  96 analog_gain_code_max                    0x0086  16
  97 analog_gain_code_step                   0x0088  16
  98 analog_gain_type                        0x008a  16
  99 analog_gain_m0                          0x008c  16
 100 analog_gain_c0                          0x008e  16
 101 analog_gain_m1                          0x0090  16
 102 analog_gain_c1                          0x0092  16
 103 analog_linear_gain_min                  0x0094  16      v1.1
 104 analog_linear_gain_max                  0x0096  16      v1.1
 105 analog_linear_gain_step_size            0x0098  16      v1.1
 106 analog_exponential_gain_min             0x009a  16      v1.1
 107 analog_exponential_gain_max             0x009c  16      v1.1
 108 analog_exponential_gain_step_size       0x009e  16      v1.1
 109
 110 # data format description registers
 111 data_format_model_type                  0x00c0  8
 112 - e     normal                          1
 113 - e     extended                        2
 114 data_format_model_subtype               0x00c1  8
 115 - f     rows                            0       3
 116 - f     columns                         4       7
 117 data_format_descriptor(n)               0x00c2  16      f
 118 - l     n                               0       15      2
 119 - f     compressed                      0       7
 120 - f     uncompressed                    8       15
 121
 122 # general set-up registers
 123 mode_select                             0x0100  8
 124 - e     software_standby                0
 125 - e     streaming                       1
 126 image_orientation                       0x0101  8
 127 - b     horizontal_mirror               0
 128 - b     vertical_flip                   1
 129 software_reset                          0x0103  8
 130 - e     off                             0
 131 - e     on                              1
 132 grouped_parameter_hold                  0x0104  8
 133 mask_corrupted_frames                   0x0105  8
 134 - e     allow                           0
 135 - e     mask                            1
 136 fast_standby_ctrl                       0x0106  8
 137 - e     complete_frames                 0
 138 - e     frame_truncation                1
 139 CCI_address_ctrl                        0x0107  8
 140 2nd_CCI_if_ctrl                         0x0108  8
 141 - b     enable                          0
 142 - b     ack                             1
 143 2nd_CCI_address_ctrl                    0x0109  8
 144 CSI_channel_identifier                  0x0110  8
 145 CSI_signaling_mode                      0x0111  8
 146 - e     csi_2_dphy                      2
 147 - e     csi_2_cphy                      3
 148 CSI_data_format                         0x0112  16
 149 CSI_lane_mode                           0x0114  8
 150 DPCM_Frame_DT                           0x011d  8
 151 Bottom_embedded_data_DT                 0x011e  8
 152 Bottom_embedded_data_VC                 0x011f  8
 153
 154 gain_mode                               0x0120  8
 155 - e     global                          0
 156 - e     alternate                       1
 157 ADC_bit_depth                           0x0121  8
 158 emb_data_ctrl                           0x0122  v1.1
 159 - b     raw8_packing_for_raw16          0
 160 - b     raw10_packing_for_raw20         1
 161 - b     raw12_packing_for_raw24         2
 162
 163 GPIO_TRIG_mode                          0x0130  8
 164 extclk_frequency_mhz                    0x0136  16      ireal
 165 temp_sensor_ctrl                        0x0138  8
 166 - b     enable                          0
 167 temp_sensor_mode                        0x0139  8
 168 temp_sensor_output                      0x013a  8
 169
 170 # integration time registers
 171 fine_integration_time                   0x0200  16
 172 coarse_integration_time                 0x0202  16
 173
 174 # analog gain registers
 175 analog_gain_code_global                 0x0204  16
 176 analog_linear_gain_global               0x0206  16      v1.1
 177 analog_exponential_gain_global          0x0208  16      v1.1
 178
 179 # digital gain registers
 180 digital_gain_global                     0x020e  16
 181
 182 # hdr control registers
 183 Short_analog_gain_global                0x0216  16
 184 Short_digital_gain_global               0x0218  16
 185
 186 HDR_mode                                0x0220  8
 187 - b     enabled                         0
 188 - b     separate_analog_gain            1
 189 - b     upscaling                       2
 190 - b     reset_sync                      3
 191 - b     timing_mode                     4
 192 - b     exposure_ctrl_direct            5
 193 - b     separate_digital_gain           6
 194 HDR_resolution_reduction                0x0221  8
 195 - f     row                             0       3
 196 - f     column                          4       7
 197 Exposure_ratio                          0x0222  8
 198 HDR_internal_bit_depth                  0x0223  8
 199 Direct_short_integration_time           0x0224  16
 200 Short_analog_linear_gain_global         0x0226  16      v1.1
 201 Short_analog_exponential_gain_global    0x0228  16      v1.1
 202
 203 # clock set-up registers
 204 vt_pix_clk_div                          0x0300  16
 205 vt_sys_clk_div                          0x0302  16
 206 pre_pll_clk_div                         0x0304  16
 207 #vt_pre_pll_clk_div                     0x0304  16
 208 pll_multiplier                          0x0306  16
 209 #vt_pll_multiplier                      0x0306  16
 210 op_pix_clk_div                          0x0308  16
 211 op_sys_clk_div                          0x030a  16
 212 op_pre_pll_clk_div                      0x030c  16
 213 op_pll_multiplier                       0x031e  16
 214 pll_mode                                0x0310  8
 215 - f                                     0       0
 216 - e     single                          0
 217 - e     dual                            1
 218 op_pix_clk_div_rev                      0x0312  16      v1.1
 219 op_sys_clk_div_rev                      0x0314  16      v1.1
 220
 221 # frame timing registers
 222 frame_length_lines                      0x0340  16
 223 line_length_pck                         0x0342  16
 224
 225 # image size registers
 226 x_addr_start                            0x0344  16
 227 y_addr_start                            0x0346  16
 228 x_addr_end                              0x0348  16
 229 y_addr_end                              0x034a  16
 230 x_output_size                           0x034c  16
 231 y_output_size                           0x034e  16
 232
 233 # timing mode registers
 234 Frame_length_ctrl                       0x0350  8
 235 - b     automatic                       0
 236 Timing_mode_ctrl                        0x0352  8
 237 - b     manual_readout                  0
 238 - b     delayed_exposure                1
 239 Start_readout_rs                        0x0353  8
 240 - b     manual_readout_start            0
 241 Frame_margin                            0x0354  16
 242
 243 # sub-sampling registers
 244 x_even_inc                              0x0380  16
 245 x_odd_inc                               0x0382  16
 246 y_even_inc                              0x0384  16
 247 y_odd_inc                               0x0386  16
 248
 249 # monochrome readout registers
 250 monochrome_en                           0x0390          v1.1
 251 - e     enabled                         0
 252
 253 # image scaling registers
 254 Scaling_mode                            0x0400  16
 255 - e     no_scaling                      0
 256 - e     horizontal                      1
 257 scale_m                                 0x0404  16
 258 scale_n                                 0x0406  16
 259 digital_crop_x_offset                   0x0408  16
 260 digital_crop_y_offset                   0x040a  16
 261 digital_crop_image_width                0x040c  16
 262 digital_crop_image_height               0x040e  16
 263
 264 # image compression registers
 265 compression_mode                        0x0500  16
 266 - e     none                            0
 267 - e     dpcm_pcm_simple                 1
 268
 269 # test pattern registers
 270 test_pattern_mode                       0x0600  16
 271 - e     none                            0
 272 - e     solid_color                     1
 273 - e     color_bars                      2
 274 - e     fade_to_grey                    3
 275 - e     pn9                             4
 276 - e     color_tile                      5
 277 test_data_red                           0x0602  16
 278 test_data_greenR                        0x0604  16
 279 test_data_blue                          0x0606  16
 280 test_data_greenB                        0x0608  16
 281 value_step_size_smooth                  0x060a  8
 282 value_step_size_quantised               0x060b  8
 283
 284 # phy configuration registers
 285 tclk_post                               0x0800  8
 286 ths_prepare                             0x0801  8
 287 ths_zero_min                            0x0802  8
 288 ths_trail                               0x0803  8
 289 tclk_trail_min                          0x0804  8
 290 tclk_prepare                            0x0805  8
 291 tclk_zero                               0x0806  8
 292 tlpx                                    0x0807  8
 293 phy_ctrl                                0x0808  8
 294 - e     auto                            0
 295 - e     UI                              1
 296 - e     manual                          2
 297 tclk_post_ex                            0x080a  16
 298 ths_prepare_ex                          0x080c  16
 299 ths_zero_min_ex                         0x080e  16
 300 ths_trail_ex                            0x0810  16
 301 tclk_trail_min_ex                       0x0812  16
 302 tclk_prepare_ex                         0x0814  16
 303 tclk_zero_ex                            0x0816  16
 304 tlpx_ex                                 0x0818  16
 305
 306 # link rate register
 307 requested_link_rate                     0x0820  32      u16.16
 308
 309 # equalization control registers
 310 DPHY_equalization_mode                  0x0824  8       v1.1
 311 - b eq2                                 0
 312 PHY_equalization_ctrl                   0x0825  8       v1.1
 313 - b enable                              0
 314
 315 # d-phy preamble control registers
 316 DPHY_preamble_ctrl                      0x0826  8       v1.1
 317 - b     enable                          0
 318 DPHY_preamble_length                    0x0826  8       v1.1
 319
 320 # d-phy spread spectrum control registers
 321 PHY_SSC_ctrl                            0x0828  8       v1.1
 322 - b     enable                          0
 323
 324 # manual lp control register
 325 manual_LP_ctrl                          0x0829  8       v1.1
 326 - b     enable                          0
 327
 328 # additional phy configuration registers
 329 twakeup                                 0x082a          v1.1
 330 tinit                                   0x082b          v1.1
 331 ths_exit                                0x082c          v1.1
 332 ths_exit_ex                             0x082e  16      v1.1
 333
 334 # phy calibration configuration registers
 335 PHY_periodic_calibration_ctrl           0x0830  8
 336 - b     frame_blanking                  0
 337 PHY_periodic_calibration_interval       0x0831  8
 338 PHY_init_calibration_ctrl               0x0832  8
 339 - b     stream_start                    0
 340 DPHY_calibration_mode                   0x0833  8       v1.1
 341 - b     also_alternate                  0
 342 CPHY_calibration_mode                   0x0834  8       v1.1
 343 - e     format_1                        0
 344 - e     format_2                        1
 345 - e     format_3                        2
 346 t3_calpreamble_length                   0x0835  8       v1.1
 347 t3_calpreamble_length_per               0x0836  8       v1.1
 348 t3_calaltseq_length                     0x0837  8       v1.1
 349 t3_calaltseq_length_per                 0x0838  8       v1.1
 350 FM2_init_seed                           0x083a  16      v1.1
 351 t3_caludefseq_length                    0x083c  16      v1.1
 352 t3_caludefseq_length_per                0x083e  16      v1.1
 353
 354 # c-phy manual control registers
 355 TGR_Preamble_Length                     0x0841  8
 356 - b     preamable_prog_seq              7
 357 - f     begin_preamble_length           0       5
 358 TGR_Post_Length                         0x0842  8
 359 - f     post_length                     0       4
 360 TGR_Preamble_Prog_Sequence(n2)          0x0843
 361 - l     n2                              0       6       1
 362 - f     symbol_n_1                      3       5
 363 - f     symbol_n                        0       2
 364 t3_prepare                              0x084e  16
 365 t3_lpx                                  0x0850  16
 366
 367 # alps control register
 368 ALPS_ctrl                               0x085a  8
 369 - b     lvlp_dphy                       0
 370 - b     lvlp_cphy                       1
 371 - b     alp_cphy                        2
 372
 373 # lrte control registers
 374 TX_REG_CSI_EPD_EN_SSP_cphy              0x0860  16
 375 TX_REG_CSI_EPD_OP_SLP_cphy              0x0862  16
 376 TX_REG_CSI_EPD_EN_SSP_dphy              0x0864  16
 377 TX_REG_CSI_EPD_OP_SLP_dphy              0x0866  16
 378 TX_REG_CSI_EPD_MISC_OPTION_cphy         0x0868          v1.1
 379 TX_REG_CSI_EPD_MISC_OPTION_dphy         0x0869          v1.1
 380
 381 # scrambling control registers
 382 Scrambling_ctrl                         0x0870
 383 - b     enabled                         0
 384 - f                                     2       3
 385 - e     1_seed_cphy                     0
 386 - e     4_seed_cphy                     3
 387 lane_seed_value(seed, lane)             0x0872  16
 388 - l     seed                            0       3       0x10
 389 - l     lane                            0       7       0x2
 390
 391 # usl control registers
 392 TX_USL_REV_ENTRY                        0x08c0  16      v1.1
 393 TX_USL_REV_Clock_Counter                0x08c2  16      v1.1
 394 TX_USL_REV_LP_Counter                   0x08c4  16      v1.1
 395 TX_USL_REV_Frame_Counter                0x08c6  16      v1.1
 396 TX_USL_REV_Chronological_Timer          0x08c8  16      v1.1
 397 TX_USL_FWD_ENTRY                        0x08ca  16      v1.1
 398 TX_USL_GPIO                             0x08cc  16      v1.1
 399 TX_USL_Operation                        0x08ce  16      v1.1
 400 - b     reset                           0
 401 TX_USL_ALP_ctrl                         0x08d0  16      v1.1
 402 - b     clock_pause                     0
 403 TX_USL_APP_BTA_ACK_TIMEOUT              0x08d2  16      v1.1
 404 TX_USL_SNS_BTA_ACK_TIMEOUT              0x08d2  16      v1.1
 405 USL_Clock_Mode_d_ctrl                   0x08d2          v1.1
 406 - b     cont_clock_standby              0
 407 - b     cont_clock_vblank               1
 408 - b     cont_clock_hblank               2
 409
 410 # binning configuration registers
 411 binning_mode                            0x0900  8
 412 binning_type                            0x0901  8
 413 binning_weighting                       0x0902  8
 414
 415 # data transfer interface registers
 416 data_transfer_if_1_ctrl                 0x0a00  8
 417 - b     enable                          0
 418 - b     write                           1
 419 - b     clear_error                     2
 420 data_transfer_if_1_status               0x0a01  8
 421 - b     read_if_ready                   0
 422 - b     write_if_ready                  1
 423 - b     data_corrupted                  2
 424 - b     improper_if_usage               3
 425 data_transfer_if_1_page_select          0x0a02  8
 426 data_transfer_if_1_data(p)              0x0a04  8       f
 427 - l     p                               0       63      1
 428
 429 # image processing and sensor correction configuration registers
 430 shading_correction_en                   0x0b00  8
 431 - b     enable                          0
 432 luminance_correction_level              0x0b01  8
 433 green_imbalance_filter_en               0x0b02  8
 434 - b     enable                          0
 435 mapped_defect_correct_en                0x0b05  8
 436 - b     enable                          0
 437 single_defect_correct_en                0x0b06  8
 438 - b     enable                          0
 439 dynamic_couplet_correct_en              0x0b08  8
 440 - b     enable                          0
 441 combined_defect_correct_en              0x0b0a  8
 442 - b     enable                          0
 443 module_specific_correction_en           0x0b0c  8
 444 - b     enable                          0
 445 dynamic_triplet_defect_correct_en       0x0b13  8
 446 - b     enable                          0
 447 NF_ctrl                                 0x0b15  8
 448 - b     luma                            0
 449 - b     chroma                          1
 450 - b     combined                        2
 451
 452 # optical black pixel readout registers
 453 OB_readout_control                      0x0b30  8
 454 - b     enable                          0
 455 - b     interleaving                    1
 456 OB_virtual_channel                      0x0b31  8
 457 OB_DT                                   0x0b32  8
 458 OB_data_format                          0x0b33  8
 459
 460 # color temperature feedback registers
 461 color_temperature                       0x0b8c  16
 462 absolute_gain_greenr                    0x0b8e  16
 463 absolute_gain_red                       0x0b90  16
 464 absolute_gain_blue                      0x0b92  16
 465 absolute_gain_greenb                    0x0b94  16
 466
 467 # cfa conversion registers
 468 CFA_conversion_ctrl                     0x0ba0          v1.1
 469 - b     bayer_conversion_enable         0
 470
 471 # flash strobe and sa strobe control registers
 472 flash_strobe_adjustment                 0x0c12  8
 473 flash_strobe_start_point                0x0c14  16
 474 tflash_strobe_delay_rs_ctrl             0x0c16  16
 475 tflash_strobe_width_high_rs_ctrl        0x0c18  16
 476 flash_mode_rs                           0x0c1a  8
 477 - b     continuous                      0
 478 - b     truncate                        1
 479 - b     async                           3
 480 flash_trigger_rs                        0x0c1b  8
 481 flash_status                            0x0c1c  8
 482 - b     retimed                         0
 483 sa_strobe_mode                          0x0c1d  8
 484 - b     continuous                      0
 485 - b     truncate                        1
 486 - b     async                           3
 487 - b     adjust_edge                     4
 488 sa_strobe_start_point                   0x0c1e  16
 489 tsa_strobe_delay_ctrl                   0x0c20  16
 490 tsa_strobe_width_ctrl                   0x0c22  16
 491 sa_strobe_trigger                       0x0c24  8
 492 sa_strobe_status                        0x0c25  8
 493 - b     retimed                         0
 494 tSA_strobe_re_delay_ctrl                0x0c30  16
 495 tSA_strobe_fe_delay_ctrl                0x0c32  16
 496
 497 # pdaf control registers
 498 PDAF_ctrl                               0x0d00  16
 499 - b     enable                          0
 500 - b     processed                       1
 501 - b     interleaved                     2
 502 - b     visible_pdaf_correction         3
 503 PDAF_VC                                 0x0d02  8
 504 PDAF_DT                                 0x0d03  8
 505 pd_x_addr_start                         0x0d04  16
 506 pd_y_addr_start                         0x0d06  16
 507 pd_x_addr_end                           0x0d08  16
 508 pd_y_addr_end                           0x0d0a  16
 509
 510 # bracketing interface configuration registers
 511 bracketing_LUT_ctrl                     0x0e00  8
 512 bracketing_LUT_mode                     0x0e01  8
 513 - b     continue_streaming              0
 514 - b     loop_mode                       1
 515 bracketing_LUT_entry_ctrl               0x0e02  8
 516 bracketing_LUT_frame(n)                 0x0e10  v1.1    f
 517 - l     n                               0       0xef    1
 518
 519 # integration time and gain parameter limit registers
 520 integration_time_capability             0x1000  16
 521 - b     fine                            0
 522 coarse_integration_time_min             0x1004  16
 523 coarse_integration_time_max_margin      0x1006  16
 524 fine_integration_time_min               0x1008  16
 525 fine_integration_time_max_margin        0x100a  16
 526
 527 # digital gain parameter limit registers
 528 digital_gain_capability                 0x1081
 529 - e     none                            0
 530 - e     global                          2
 531 digital_gain_min                        0x1084  16
 532 digital_gain_max                        0x1086  16
 533 digital_gain_step_size                  0x1088  16
 534
 535 # data pedestal capability registers
 536 Pedestal_capability                     0x10e0  8       v1.1
 537
 538 # adc capability registers
 539 ADC_capability                          0x10f0  8
 540 - b     bit_depth_ctrl                  0
 541 ADC_bit_depth_capability                0x10f4  32      v1.1
 542
 543 # video timing parameter limit registers
 544 min_ext_clk_freq_mhz                    0x1100  32      float_ireal
 545 max_ext_clk_freq_mhz                    0x1104  32      float_ireal
 546 min_pre_pll_clk_div                     0x1108  16
 547 # min_vt_pre_pll_clk_div                        0x1108  16
 548 max_pre_pll_clk_div                     0x110a  16
 549 # max_vt_pre_pll_clk_div                        0x110a  16
 550 min_pll_ip_clk_freq_mhz                 0x110c  32      float_ireal
 551 # min_vt_pll_ip_clk_freq_mhz            0x110c  32      float_ireal
 552 max_pll_ip_clk_freq_mhz                 0x1110  32      float_ireal
 553 # max_vt_pll_ip_clk_freq_mhz            0x1110  32      float_ireal
 554 min_pll_multiplier                      0x1114  16
 555 # min_vt_pll_multiplier                 0x1114  16
 556 max_pll_multiplier                      0x1116  16
 557 # max_vt_pll_multiplier                 0x1116  16
 558 min_pll_op_clk_freq_mhz                 0x1118  32      float_ireal
 559 max_pll_op_clk_freq_mhz                 0x111c  32      float_ireal
 560
 561 # video timing set-up capability registers
 562 min_vt_sys_clk_div                      0x1120  16
 563 max_vt_sys_clk_div                      0x1122  16
 564 min_vt_sys_clk_freq_mhz                 0x1124  32      float_ireal
 565 max_vt_sys_clk_freq_mhz                 0x1128  32      float_ireal
 566 min_vt_pix_clk_freq_mhz                 0x112c  32      float_ireal
 567 max_vt_pix_clk_freq_mhz                 0x1130  32      float_ireal
 568 min_vt_pix_clk_div                      0x1134  16
 569 max_vt_pix_clk_div                      0x1136  16
 570 clock_calculation                       0x1138
 571 - b     lane_speed                      0
 572 - b     link_decoupled                  1
 573 - b     dual_pll_op_sys_ddr             2
 574 - b     dual_pll_op_pix_ddr             3
 575 num_of_vt_lanes                         0x1139
 576 num_of_op_lanes                         0x113a
 577 op_bits_per_lane                        0x113b  8       v1.1
 578
 579 # frame timing parameter limits
 580 min_frame_length_lines                  0x1140  16
 581 max_frame_length_lines                  0x1142  16
 582 min_line_length_pck                     0x1144  16
 583 max_line_length_pck                     0x1146  16
 584 min_line_blanking_pck                   0x1148  16
 585 min_frame_blanking_lines                0x114a  16
 586 min_line_length_pck_step_size           0x114c
 587 timing_mode_capability                  0x114d
 588 - b     auto_frame_length               0
 589 - b     rolling_shutter_manual_readout  2
 590 - b     delayed_exposure_start          3
 591 - b     manual_exposure_embedded_data   4
 592 frame_margin_max_value                  0x114e  16
 593 frame_margin_min_value                  0x1150
 594 gain_delay_type                         0x1151
 595 - e     fixed                           0
 596 - e     variable                        1
 597
 598 # output clock set-up capability registers
 599 min_op_sys_clk_div                      0x1160  16
 600 max_op_sys_clk_div                      0x1162  16
 601 min_op_sys_clk_freq_mhz                 0x1164  32      float_ireal
 602 max_op_sys_clk_freq_mhz                 0x1168  32      float_ireal
 603 min_op_pix_clk_div                      0x116c  16
 604 max_op_pix_clk_div                      0x116e  16
 605 min_op_pix_clk_freq_mhz                 0x1170  32      float_ireal
 606 max_op_pix_clk_freq_mhz                 0x1174  32      float_ireal
 607
 608 # image size parameter limit registers
 609 x_addr_min                              0x1180  16
 610 y_addr_min                              0x1182  16
 611 x_addr_max                              0x1184  16
 612 y_addr_max                              0x1186  16
 613 min_x_output_size                       0x1188  16
 614 min_y_output_size                       0x118a  16
 615 max_x_output_size                       0x118c  16
 616 max_y_output_size                       0x118e  16
 617
 618 x_addr_start_div_constant               0x1190          v1.1
 619 y_addr_start_div_constant               0x1191          v1.1
 620 x_addr_end_div_constant                 0x1192          v1.1
 621 y_addr_end_div_constant                 0x1193          v1.1
 622 x_size_div                              0x1194          v1.1
 623 y_size_div                              0x1195          v1.1
 624 x_output_div                            0x1196          v1.1
 625 y_output_div                            0x1197          v1.1
 626 non_flexible_resolution_support         0x1198          v1.1
 627 - b     new_pix_addr                    0
 628 - b     new_output_res                  1
 629 - b     output_crop_no_pad              2
 630 - b     output_size_lane_dep            3
 631
 632 min_op_pre_pll_clk_div                  0x11a0  16
 633 max_op_pre_pll_clk_div                  0x11a2  16
 634 min_op_pll_ip_clk_freq_mhz              0x11a4  32      float_ireal
 635 max_op_pll_ip_clk_freq_mhz              0x11a8  32      float_ireal
 636 min_op_pll_multiplier                   0x11ac  16
 637 max_op_pll_multiplier                   0x11ae  16
 638 min_op_pll_op_clk_freq_mhz              0x11b0  32      float_ireal
 639 max_op_pll_op_clk_freq_mhz              0x11b4  32      float_ireal
 640 clock_tree_pll_capability               0x11b8  8
 641 - b     dual_pll                        0
 642 - b     single_pll                      1
 643 - b     ext_divider                     2
 644 - b     flexible_op_pix_clk_div         3
 645 clock_capa_type_capability              0x11b9  v1.1
 646 - b     ireal                           0
 647
 648 # sub-sampling parameters limit registers
 649 min_even_inc                            0x11c0  16
 650 min_odd_inc                             0x11c2  16
 651 max_even_inc                            0x11c4  16
 652 max_odd_inc                             0x11c6  16
 653 aux_subsamp_capability                  0x11c8          v1.1
 654 - b     factor_power_of_2               1
 655 aux_subsamp_mono_capability             0x11c9          v1.1
 656 - b     factor_power_of_2               1
 657 monochrome_capability                   0x11ca          v1.1
 658 - e     inc_odd                         0
 659 - e     inc_even                        1
 660 pixel_readout_capability                0x11cb          v1.1
 661 - e     bayer                           0
 662 - e     monochrome                      1
 663 - e     bayer_and_mono                  2
 664 min_even_inc_mono                       0x11cc  16      v1.1
 665 max_even_inc_mono                       0x11ce  16      v1.1
 666 min_odd_inc_mono                        0x11d0  16      v1.1
 667 max_odd_inc_mono                        0x11d2  16      v1.1
 668 min_even_inc_bc2                        0x11d4  16      v1.1
 669 max_even_inc_bc2                        0x11d6  16      v1.1
 670 min_odd_inc_bc2                         0x11d8  16      v1.1
 671 max_odd_inc_bc2                         0x11da  16      v1.1
 672 min_even_inc_mono_bc2                   0x11dc  16      v1.1
 673 max_even_inc_mono_bc2                   0x11de  16      v1.1
 674 min_odd_inc_mono_bc2                    0x11f0  16      v1.1
 675 max_odd_inc_mono_bc2                    0x11f2  16      v1.1
 676
 677 # image scaling limit parameters
 678 scaling_capability                      0x1200  16
 679 - e     none                            0
 680 - e     horizontal                      1
 681 - e     reserved                        2
 682 scaler_m_min                            0x1204  16
 683 scaler_m_max                            0x1206  16
 684 scaler_n_min                            0x1208  16
 685 scaler_n_max                            0x120a  16
 686 digital_crop_capability                 0x120e
 687 - e     none                            0
 688 - e     input_crop                      1
 689
 690 # hdr limit registers
 691 hdr_capability_1                        0x1210
 692 - b     2x2_binning                     0
 693 - b     combined_analog_gain            1
 694 - b     separate_analog_gain            2
 695 - b     upscaling                       3
 696 - b     reset_sync                      4
 697 - b     direct_short_exp_timing         5
 698 - b     direct_short_exp_synthesis      6
 699 min_hdr_bit_depth                       0x1211
 700 hdr_resolution_sub_types                0x1212
 701 hdr_resolution_sub_type(n)              0x1213
 702 - l     n                               0       1       1
 703 - f     row                             0       3
 704 - f     column                          4       7
 705 hdr_capability_2                        0x121b
 706 - b     combined_digital_gain           0
 707 - b     separate_digital_gain           1
 708 - b     timing_mode                     3
 709 - b     synthesis_mode                  4
 710 max_hdr_bit_depth                       0x121c
 711
 712 # usl capability register
 713 usl_support_capability                  0x1230          v1.1
 714 - b     clock_tree                      0
 715 - b     rev_clock_tree                  1
 716 - b     rev_clock_calc                  2
 717 usl_clock_mode_d_capability             0x1231          v1.1
 718 - b     cont_clock_standby              0
 719 - b     cont_clock_vblank               1
 720 - b     cont_clock_hblank               2
 721 - b     noncont_clock_standby           3
 722 - b     noncont_clock_vblank            4
 723 - b     noncont_clock_hblank            5
 724 min_op_sys_clk_div_rev                  0x1234          v1.1
 725 max_op_sys_clk_div_rev                  0x1236          v1.1
 726 min_op_pix_clk_div_rev                  0x1238          v1.1
 727 max_op_pix_clk_div_rev                  0x123a          v1.1
 728 min_op_sys_clk_freq_rev_mhz             0x123c  32      v1.1    float_ireal
 729 max_op_sys_clk_freq_rev_mhz             0x1240  32      v1.1    float_ireal
 730 min_op_pix_clk_freq_rev_mhz             0x1244  32      v1.1    float_ireal
 731 max_op_pix_clk_freq_rev_mhz             0x1248  32      v1.1    float_ireal
 732 max_bitrate_rev_d_mode_mbps             0x124c  32      v1.1    ireal
 733 max_symrate_rev_c_mode_msps             0x1250  32      v1.1    ireal
 734
 735 # image compression capability registers
 736 compression_capability                  0x1300
 737 - b     dpcm_pcm_simple                 0
 738
 739 # test mode capability registers
 740 test_mode_capability                    0x1310  16
 741 - b     solid_color                     0
 742 - b     color_bars                      1
 743 - b     fade_to_grey                    2
 744 - b     pn9                             3
 745 - b     color_tile                      5
 746 pn9_data_format1                        0x1312
 747 pn9_data_format2                        0x1313
 748 pn9_data_format3                        0x1314
 749 pn9_data_format4                        0x1315
 750 pn9_misc_capability                     0x1316
 751 - f     num_pixels                      0       2
 752 - b     compression                     3
 753 test_pattern_capability                 0x1317  v1.1
 754 - b     no_repeat                       1
 755 pattern_size_div_m1                     0x1318  v1.1
 756
 757 # fifo capability registers
 758 fifo_support_capability                 0x1502
 759 - e     none                            0
 760 - e     derating                        1
 761 - e     derating_overrating             2
 762
 763 # csi-2 capability registers
 764 phy_ctrl_capability                     0x1600
 765 - b     auto_phy_ctl                    0
 766 - b     ui_phy_ctl                      1
 767 - b     dphy_time_ui_reg_1_ctl          2
 768 - b     dphy_time_ui_reg_2_ctl          3
 769 - b     dphy_time_ctl                   4
 770 - b     dphy_ext_time_ui_reg_1_ctl      5
 771 - b     dphy_ext_time_ui_reg_2_ctl      6
 772 - b     dphy_ext_time_ctl               7
 773 csi_dphy_lane_mode_capability           0x1601
 774 - b     1_lane                          0
 775 - b     2_lane                          1
 776 - b     3_lane                          2
 777 - b     4_lane                          3
 778 - b     5_lane                          4
 779 - b     6_lane                          5
 780 - b     7_lane                          6
 781 - b     8_lane                          7
 782 csi_signaling_mode_capability           0x1602
 783 - b     csi_dphy                        2
 784 - b     csi_cphy                        3
 785 fast_standby_capability                 0x1603
 786 - e     no_frame_truncation             0
 787 - e     frame_truncation                1
 788 csi_address_control_capability          0x1604
 789 - b     cci_addr_change                 0
 790 - b     2nd_cci_addr                    1
 791 - b     sw_changeable_2nd_cci_addr      2
 792 data_type_capability                    0x1605
 793 - b     dpcm_programmable               0
 794 - b     bottom_embedded_dt_programmable 1
 795 - b     bottom_embedded_vc_programmable 2
 796 - b     ext_vc_range                    3
 797 csi_cphy_lane_mode_capability           0x1606
 798 - b     1_lane                          0
 799 - b     2_lane                          1
 800 - b     3_lane                          2
 801 - b     4_lane                          3
 802 - b     5_lane                          4
 803 - b     6_lane                          5
 804 - b     7_lane                          6
 805 - b     8_lane                          7
 806 emb_data_capability                     0x1607  v1.1
 807 - b     two_bytes_per_raw16             0
 808 - b     two_bytes_per_raw20             1
 809 - b     two_bytes_per_raw24             2
 810 - b     no_one_byte_per_raw16           3
 811 - b     no_one_byte_per_raw20           4
 812 - b     no_one_byte_per_raw24           5
 813 max_per_lane_bitrate_lane_d_mode_mbps(n)        0x1608  32      ireal
 814 - l     n                               0       7       4       4,0x32
 815 temp_sensor_capability                  0x1618
 816 - b     supported                       0
 817 - b     CCS_format                      1
 818 - b     reset_0x80                      2
 819 max_per_lane_bitrate_lane_c_mode_mbps(n)        0x161a  32      ireal
 820 - l     n                               0       7       4       4,0x30
 821 dphy_equalization_capability            0x162b
 822 - b     equalization_ctrl               0
 823 - b     eq1                             1
 824 - b     eq2                             2
 825 cphy_equalization_capability            0x162c
 826 - b     equalization_ctrl               0
 827 dphy_preamble_capability                0x162d
 828 - b     preamble_seq_ctrl               0
 829 dphy_ssc_capability                     0x162e
 830 - b     supported                       0
 831 cphy_calibration_capability             0x162f
 832 - b     manual                          0
 833 - b     manual_streaming                1
 834 - b     format_1_ctrl                   2
 835 - b     format_2_ctrl                   3
 836 - b     format_3_ctrl                   4
 837 dphy_calibration_capability             0x1630
 838 - b     manual                          0
 839 - b     manual_streaming                1
 840 - b     alternate_seq                   2
 841 phy_ctrl_capability_2                   0x1631
 842 - b     tgr_length                      0
 843 - b     tgr_preamble_prog_seq           1
 844 - b     extra_cphy_manual_timing        2
 845 - b     clock_based_manual_cdphy        3
 846 - b     clock_based_manual_dphy         4
 847 - b     clock_based_manual_cphy         5
 848 - b     manual_lp_dphy                  6
 849 - b     manual_lp_cphy                  7
 850 lrte_cphy_capability                    0x1632
 851 - b     pdq_short                       0
 852 - b     spacer_short                    1
 853 - b     pdq_long                        2
 854 - b     spacer_long                     3
 855 - b     spacer_no_pdq                   4
 856 lrte_dphy_capability                    0x1633
 857 - b     pdq_short_opt1                  0
 858 - b     spacer_short_opt1               1
 859 - b     pdq_long_opt1                   2
 860 - b     spacer_long_opt1                3
 861 - b     spacer_short_opt2               4
 862 - b     spacer_long_opt2                5
 863 - b     spacer_no_pdq_opt1              6
 864 - b     spacer_variable_opt2            7
 865 alps_capability_dphy                    0x1634
 866 - e     lvlp_not_supported              0       0x3
 867 - e     lvlp_supported                  1       0x3
 868 - e     controllable_lvlp               2       0x3
 869 alps_capability_cphy                    0x1635
 870 - e     lvlp_not_supported              0       0x3
 871 - e     lvlp_supported                  1       0x3
 872 - e     controllable_lvlp               2       0x3
 873 - e     alp_not_supported               0xc     0xc
 874 - e     alp_supported                   0xd     0xc
 875 - e     controllable_alp                0xe     0xc
 876 scrambling_capability                   0x1636
 877 - b     scrambling_supported            0
 878 - f     max_seeds_per_lane_c            1       2
 879 - e     1                               0
 880 - e     4                               3
 881 - f     num_seed_regs                   3       5
 882 - e     0                               0
 883 - e     1                               1
 884 - e     4                               4
 885 - b     num_seed_per_lane               6
 886 dphy_manual_constant                    0x1637
 887 cphy_manual_constant                    0x1638
 888 CSI2_interface_capability_misc          0x1639  v1.1
 889 - b     eotp_short_pkt_opt2             0
 890 PHY_ctrl_capability_3                   0x165c  v1.1
 891 - b     dphy_timing_not_multiple        0
 892 - b     dphy_min_timing_value_1         1
 893 - b     twakeup_supported               2
 894 - b     tinit_supported                 3
 895 - b     ths_exit_supported              4
 896 - b     cphy_timing_not_multiple        5
 897 - b     cphy_min_timing_value_1         6
 898 dphy_sf                                 0x165d  v1.1
 899 cphy_sf                                 0x165e  v1.1
 900 - f     twakeup                         0       3
 901 - f     tinit                           4       7
 902 dphy_limits_1                           0x165f  v1.1
 903 - f     ths_prepare                     0       3
 904 - f     ths_zero                        4       7
 905 dphy_limits_2                           0x1660  v1.1
 906 - f     ths_trail                       0       3
 907 - f     tclk_trail_min                  4       7
 908 dphy_limits_3                           0x1661  v1.1
 909 - f     tclk_prepare                    0       3
 910 - f     tclk_zero                       4       7
 911 dphy_limits_4                           0x1662  v1.1
 912 - f     tclk_post                       0       3
 913 - f     tlpx                            4       7
 914 dphy_limits_5                           0x1663  v1.1
 915 - f     ths_exit                        0       3
 916 - f     twakeup                         4       7
 917 dphy_limits_6                           0x1664  v1.1
 918 - f     tinit                           0       3
 919 cphy_limits_1                           0x1665  v1.1
 920 - f     t3_prepare_max                  0       3
 921 - f     t3_lpx_max                      4       7
 922 cphy_limits_2                           0x1666  v1.1
 923 - f     ths_exit_max                    0       3
 924 - f     twakeup_max                     4       7
 925 cphy_limits_3                           0x1667  v1.1
 926 - f     tinit_max                       0       3
 927
 928 # binning capability registers
 929 min_frame_length_lines_bin              0x1700  16
 930 max_frame_length_lines_bin              0x1702  16
 931 min_line_length_pck_bin                 0x1704  16
 932 max_line_length_pck_bin                 0x1706  16
 933 min_line_blanking_pck_bin               0x1708  16
 934 fine_integration_time_min_bin           0x170a  16
 935 fine_integration_time_max_margin_bin    0x170c  16
 936 binning_capability                      0x1710
 937 - e     unsupported                     0
 938 - e     binning_then_subsampling        1
 939 - e     subsampling_then_binning        2
 940 binning_weighting_capability            0x1711
 941 - b     averaged                        0
 942 - b     summed                          1
 943 - b     bayer_corrected                 2
 944 - b     module_specific_weight          3
 945 binning_sub_types                       0x1712
 946 binning_sub_type(n)                     0x1713
 947 - l     n                               0       63      1
 948 - f     row                             0       3
 949 - f     column                          4       7
 950 binning_weighting_mono_capability       0x1771  v1.1
 951 - b     averaged                        0
 952 - b     summed                          1
 953 - b     bayer_corrected                 2
 954 - b     module_specific_weight          3
 955 binning_sub_types_mono                  0x1772  v1.1
 956 binning_sub_type_mono(n)                0x1773  v1.1    f
 957 - l     n                               0       63      1
 958
 959 # data transfer interface capability registers
 960 data_transfer_if_capability             0x1800
 961 - b     supported                       0
 962 - b     polling                         2
 963
 964 # sensor correction capability registers
 965 shading_correction_capability           0x1900
 966 - b     color_shading                   0
 967 - b     luminance_correction            1
 968 green_imbalance_capability              0x1901
 969 - b     supported                       0
 970 module_specific_correction_capability   0x1903
 971 defect_correction_capability            0x1904  16
 972 - b     mapped_defect                   0
 973 - b     dynamic_couplet                 2
 974 - b     dynamic_single                  5
 975 - b     combined_dynamic                8
 976 defect_correction_capability_2          0x1906  16
 977 - b     dynamic_triplet                 3
 978 nf_capability                           0x1908
 979 - b     luma                            0
 980 - b     chroma                          1
 981 - b     combined                        2
 982
 983 # optical black readout capability registers
 984 ob_readout_capability                   0x1980
 985 - b     controllable_readout            0
 986 - b     visible_pixel_readout           1
 987 - b     different_vc_readout            2
 988 - b     different_dt_readout            3
 989 - b     prog_data_format                4
 990
 991 # color feedback capability registers
 992 color_feedback_capability               0x1987
 993 - b     kelvin                          0
 994 - b     awb_gain                        1
 995
 996 # cfa pattern capability registers
 997 CFA_pattern_capability                  0x1990  v1.1
 998 - e     bayer                           0
 999 - e     monochrome                      1
1000 - e     4x4_quad_bayer                  2
1001 - e     vendor_specific                 3
1002 CFA_pattern_conversion_capability       0x1991  v1.1
1003 - b     bayer                           0
1004
1005 # timer capability registers
1006 flash_mode_capability                   0x1a02
1007 - b     single_strobe                   0
1008 sa_strobe_mode_capability               0x1a03
1009 - b     fixed_width                     0
1010 - b     edge_ctrl                       1
1011
1012 # soft reset capability registers
1013 reset_max_delay                         0x1a10  v1.1
1014 reset_min_time                          0x1a11  v1.1
1015
1016 # pdaf capability registers
1017 pdaf_capability_1                       0x1b80
1018 - b     supported                       0
1019 - b     processed_bottom_embedded       1
1020 - b     processed_interleaved           2
1021 - b     raw_bottom_embedded             3
1022 - b     raw_interleaved                 4
1023 - b     visible_pdaf_correction         5
1024 - b     vc_interleaving                 6
1025 - b     dt_interleaving                 7
1026 pdaf_capability_2                       0x1b81
1027 - b     ROI                             0
1028 - b     after_digital_crop              1
1029 - b     ctrl_retimed                    2
1030
1031 # bracketing interface capability registers
1032 bracketing_lut_capability_1             0x1c00
1033 - b     coarse_integration              0
1034 - b     global_analog_gain              1
1035 - b     flash                           4
1036 - b     global_digital_gain             5
1037 - b     alternate_global_analog_gain    6
1038 bracketing_lut_capability_2             0x1c01
1039 - b     single_bracketing_mode          0
1040 - b     looped_bracketing_mode          1
1041 bracketing_lut_size                     0x1c02