Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
   8
   9 maintainers:
  10   - Manu Gautam <mgautam@codeaurora.org>
  11
  12 properties:
  13   compatible:
  14     items:
  15       - enum:
  16           - qcom,msm8996-dwc3
  17           - qcom,msm8998-dwc3
  18           - qcom,sc7180-dwc3
  19           - qcom,sc7280-dwc3
  20           - qcom,sdm660-dwc3
  21           - qcom,sdm845-dwc3
  22           - qcom,sdx55-dwc3
  23           - qcom,sm4250-dwc3
  24           - qcom,sm6115-dwc3
  25           - qcom,sm8150-dwc3
  26           - qcom,sm8250-dwc3
  27           - qcom,sm8350-dwc3
  28       - const: qcom,dwc3
  29
  30   reg:
  31     description: Offset and length of register set for QSCRATCH wrapper
  32     maxItems: 1
  33
  34   "#address-cells":
  35     enum: [ 1, 2 ]
  36
  37   "#size-cells":
  38     enum: [ 1, 2 ]
  39
  40   ranges: true
  41
  42   power-domains:
  43     description: specifies a phandle to PM domain provider node
  44     maxItems: 1
  45
  46   clocks:
  47     description:
  48       A list of phandle and clock-specifier pairs for the clocks
  49       listed in clock-names.
  50     items:
  51       - description: System Config NOC clock.
  52       - description: Master/Core clock, has to be >= 125 MHz
  53           for SS operation and >= 60MHz for HS operation.
  54       - description: System bus AXI clock.
  55       - description: Mock utmi clock needed for ITP/SOF generation
  56           in host mode. Its frequency should be 19.2MHz.
  57       - description: Sleep clock, used for wakeup when
  58           USB3 core goes into low power mode (U3).
  59
  60   clock-names:
  61     items:
  62       - const: cfg_noc
  63       - const: core
  64       - const: iface
  65       - const: mock_utmi
  66       - const: sleep
  67
  68   assigned-clocks:
  69     items:
  70       - description: Phandle and clock specifier of MOCK_UTMI_CLK.
  71       - description: Phandle and clock specifoer of MASTER_CLK.
  72
  73   assigned-clock-rates:
  74     items:
  75       - description: Must be 19.2MHz (19200000).
  76       - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
  77   resets:
  78     maxItems: 1
  79
  80   interconnects:
  81     maxItems: 2
  82
  83   interconnect-names:
  84     items:
  85       - const: usb-ddr
  86       - const: apps-usb
  87
  88   interrupts:
  89     items:
  90       - description: The interrupt that is asserted
  91           when a wakeup event is received on USB2 bus.
  92       - description: The interrupt that is asserted
  93           when a wakeup event is received on USB3 bus.
  94       - description: Wakeup event on DM line.
  95       - description: Wakeup event on DP line.
  96
  97   interrupt-names:
  98     items:
  99       - const: hs_phy_irq
 100       - const: ss_phy_irq
 101       - const: dm_hs_phy_irq
 102       - const: dp_hs_phy_irq
 103
 104   qcom,select-utmi-as-pipe-clk:
 105     description:
 106       If present, disable USB3 pipe_clk requirement.
 107       Used when dwc3 operates without SSPHY and only
 108       HS/FS/LS modes are supported.
 109     type: boolean
 110
 111 # Required child node:
 112
 113 patternProperties:
 114   "^usb@[0-9a-f]+$":
 115     $ref: snps,dwc3.yaml#
 116
 117 required:
 118   - compatible
 119   - reg
 120   - "#address-cells"
 121   - "#size-cells"
 122   - ranges
 123   - power-domains
 124   - clocks
 125   - clock-names
 126   - interrupts
 127   - interrupt-names
 128
 129 additionalProperties: false
 130
 131 examples:
 132   - |
 133     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 134     #include <dt-bindings/interrupt-controller/arm-gic.h>
 135     #include <dt-bindings/interrupt-controller/irq.h>
 136     soc {
 137         #address-cells = <2>;
 138         #size-cells = <2>;
 139
 140         usb@a6f8800 {
 141             compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
 142             reg = <0 0x0a6f8800 0 0x400>;
 143
 144             #address-cells = <2>;
 145             #size-cells = <2>;
 146             ranges;
 147             clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
 148                      <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 149                      <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
 150                      <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 151                      <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
 152             clock-names = "cfg_noc", "core", "iface", "mock_utmi",
 153                       "sleep";
 154
 155             assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 156                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 157             assigned-clock-rates = <19200000>, <150000000>;
 158
 159             interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 160                          <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
 161                          <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
 162                          <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
 163             interrupt-names = "hs_phy_irq", "ss_phy_irq",
 164                           "dm_hs_phy_irq", "dp_hs_phy_irq";
 165
 166             power-domains = <&gcc USB30_PRIM_GDSC>;
 167
 168             resets = <&gcc GCC_USB30_PRIM_BCR>;
 169
 170             usb@a600000 {
 171                 compatible = "snps,dwc3";
 172                 reg = <0 0x0a600000 0 0xcd00>;
 173                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 174                 iommus = <&apps_smmu 0x740 0>;
 175                 snps,dis_u2_susphy_quirk;
 176                 snps,dis_enblslpm_quirk;
 177                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
 178                 phy-names = "usb2-phy", "usb3-phy";
 179             };
 180         };
 181     };