Documentation/devicetree/bindings/usb/qcom,dwc3.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Qualcomm SuperSpeed DWC3 USB SoC controller
   8
   9 maintainers:
  10   - Manu Gautam <mgautam@codeaurora.org>
  11
  12 properties:
  13   compatible:
  14     items:
  15       - enum:
  16           - qcom,msm8996-dwc3
  17           - qcom,msm8998-dwc3
  18           - qcom,sc7180-dwc3
  19           - qcom,sc7280-dwc3
  20           - qcom,sdm845-dwc3
  21           - qcom,sdx55-dwc3
  22           - qcom,sm4250-dwc3
  23           - qcom,sm6115-dwc3
  24           - qcom,sm8150-dwc3
  25           - qcom,sm8250-dwc3
  26           - qcom,sm8350-dwc3
  27       - const: qcom,dwc3
  28
  29   reg:
  30     description: Offset and length of register set for QSCRATCH wrapper
  31     maxItems: 1
  32
  33   "#address-cells":
  34     enum: [ 1, 2 ]
  35
  36   "#size-cells":
  37     enum: [ 1, 2 ]
  38
  39   ranges: true
  40
  41   power-domains:
  42     description: specifies a phandle to PM domain provider node
  43     maxItems: 1
  44
  45   clocks:
  46     description:
  47       A list of phandle and clock-specifier pairs for the clocks
  48       listed in clock-names.
  49     items:
  50       - description: System Config NOC clock.
  51       - description: Master/Core clock, has to be >= 125 MHz
  52           for SS operation and >= 60MHz for HS operation.
  53       - description: System bus AXI clock.
  54       - description: Mock utmi clock needed for ITP/SOF generation
  55           in host mode. Its frequency should be 19.2MHz.
  56       - description: Sleep clock, used for wakeup when
  57           USB3 core goes into low power mode (U3).
  58
  59   clock-names:
  60     items:
  61       - const: cfg_noc
  62       - const: core
  63       - const: iface
  64       - const: mock_utmi
  65       - const: sleep
  66
  67   assigned-clocks:
  68     items:
  69       - description: Phandle and clock specifier of MOCK_UTMI_CLK.
  70       - description: Phandle and clock specifoer of MASTER_CLK.
  71
  72   assigned-clock-rates:
  73     items:
  74       - description: Must be 19.2MHz (19200000).
  75       - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
  76   resets:
  77     maxItems: 1
  78
  79   interconnects:
  80     maxItems: 2
  81
  82   interconnect-names:
  83     items:
  84       - const: usb-ddr
  85       - const: apps-usb
  86
  87   interrupts:
  88     items:
  89       - description: The interrupt that is asserted
  90           when a wakeup event is received on USB2 bus.
  91       - description: The interrupt that is asserted
  92           when a wakeup event is received on USB3 bus.
  93       - description: Wakeup event on DM line.
  94       - description: Wakeup event on DP line.
  95
  96   interrupt-names:
  97     items:
  98       - const: hs_phy_irq
  99       - const: ss_phy_irq
 100       - const: dm_hs_phy_irq
 101       - const: dp_hs_phy_irq
 102
 103   qcom,select-utmi-as-pipe-clk:
 104     description:
 105       If present, disable USB3 pipe_clk requirement.
 106       Used when dwc3 operates without SSPHY and only
 107       HS/FS/LS modes are supported.
 108     type: boolean
 109
 110 # Required child node:
 111
 112 patternProperties:
 113   "^usb@[0-9a-f]+$":
 114     $ref: snps,dwc3.yaml#
 115
 116 required:
 117   - compatible
 118   - reg
 119   - "#address-cells"
 120   - "#size-cells"
 121   - ranges
 122   - power-domains
 123   - clocks
 124   - clock-names
 125   - interrupts
 126   - interrupt-names
 127
 128 additionalProperties: false
 129
 130 examples:
 131   - |
 132     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 133     #include <dt-bindings/interrupt-controller/arm-gic.h>
 134     #include <dt-bindings/interrupt-controller/irq.h>
 135     soc {
 136         #address-cells = <2>;
 137         #size-cells = <2>;
 138
 139         usb@a6f8800 {
 140             compatible = "qcom,sdm845-dwc3", "qcom,dwc3";
 141             reg = <0 0x0a6f8800 0 0x400>;
 142
 143             #address-cells = <2>;
 144             #size-cells = <2>;
 145             ranges;
 146             clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
 147                      <&gcc GCC_USB30_PRIM_MASTER_CLK>,
 148                      <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
 149                      <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 150                      <&gcc GCC_USB30_PRIM_SLEEP_CLK>;
 151             clock-names = "cfg_noc", "core", "iface", "mock_utmi",
 152                       "sleep";
 153
 154             assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
 155                           <&gcc GCC_USB30_PRIM_MASTER_CLK>;
 156             assigned-clock-rates = <19200000>, <150000000>;
 157
 158             interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>,
 159                          <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>,
 160                          <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>,
 161                          <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
 162             interrupt-names = "hs_phy_irq", "ss_phy_irq",
 163                           "dm_hs_phy_irq", "dp_hs_phy_irq";
 164
 165             power-domains = <&gcc USB30_PRIM_GDSC>;
 166
 167             resets = <&gcc GCC_USB30_PRIM_BCR>;
 168
 169             usb@a600000 {
 170                 compatible = "snps,dwc3";
 171                 reg = <0 0x0a600000 0 0xcd00>;
 172                 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
 173                 iommus = <&apps_smmu 0x740 0>;
 174                 snps,dis_u2_susphy_quirk;
 175                 snps,dis_enblslpm_quirk;
 176                 phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
 177                 phy-names = "usb2-phy", "usb3-phy";
 178             };
 179         };
 180     };