Documentation/devicetree/bindings/sound/nvidia,tegra-audio-graph-card.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/sound/nvidia,tegra-audio-graph-card.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Audio Graph based Tegra sound card driver
   8
   9 description: |
  10   This is based on generic audio graph card driver along with additional
  11   customizations for Tegra platforms. It uses the same bindings with
  12   additional standard clock DT bindings required for Tegra.
  13
  14 maintainers:
  15   - Jon Hunter <jonathanh@nvidia.com>
  16   - Sameer Pujar <spujar@nvidia.com>
  17
  18 allOf:
  19   - $ref: audio-graph.yaml#
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - nvidia,tegra210-audio-graph-card
  25       - nvidia,tegra186-audio-graph-card
  26
  27   clocks:
  28     minItems: 2
  29
  30   clock-names:
  31     items:
  32       - const: pll_a
  33       - const: plla_out0
  34
  35   assigned-clocks:
  36     minItems: 1
  37     maxItems: 3
  38
  39   assigned-clock-parents:
  40     minItems: 1
  41     maxItems: 3
  42
  43   assigned-clock-rates:
  44     minItems: 1
  45     maxItems: 3
  46
  47   iommus:
  48     maxItems: 1
  49
  50 required:
  51   - clocks
  52   - clock-names
  53   - assigned-clocks
  54   - assigned-clock-parents
  55
  56 unevaluatedProperties: false
  57
  58 examples:
  59   - |
  60     #include<dt-bindings/clock/tegra210-car.h>
  61
  62     tegra_sound {
  63         compatible = "nvidia,tegra210-audio-graph-card";
  64
  65         clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
  66                  <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
  67         clock-names = "pll_a", "plla_out0";
  68
  69         assigned-clocks = <&tegra_car TEGRA210_CLK_PLL_A>,
  70                           <&tegra_car TEGRA210_CLK_PLL_A_OUT0>,
  71                           <&tegra_car TEGRA210_CLK_EXTERN1>;
  72         assigned-clock-parents = <0>, <0>, <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
  73         assigned-clock-rates = <368640000>, <49152000>, <12288000>;
  74
  75         dais = /* FE */
  76                <&admaif1_port>,
  77                /* Router */
  78                <&xbar_i2s1_port>,
  79                /* I/O DAP Ports */
  80                <&i2s1_port>;
  81
  82         label = "jetson-tx1-ape";
  83     };
  84
  85     // The ports are defined for AHUB and its child devices.
  86     ahub@702d0800 {
  87         compatible = "nvidia,tegra210-ahub";
  88         reg = <0x702d0800 0x800>;
  89         clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
  90         clock-names = "ahub";
  91         assigned-clocks = <&tegra_car TEGRA210_CLK_D_AUDIO>;
  92         assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
  93         #address-cells = <1>;
  94         #size-cells = <1>;
  95         ranges = <0x702d0000 0x702d0000 0x0000e400>;
  96
  97         ports {
  98             #address-cells = <1>;
  99             #size-cells = <0>;
 100
 101             port@0 {
 102                 reg = <0x0>;
 103                 xbar_admaif1_ep: endpoint {
 104                     remote-endpoint = <&admaif1_ep>;
 105                 };
 106             };
 107
 108             // ...
 109
 110             xbar_i2s1_port: port@a {
 111                 reg = <0xa>;
 112                 xbar_i2s1_ep: endpoint {
 113                     remote-endpoint = <&i2s1_cif_ep>;
 114                 };
 115             };
 116         };
 117
 118         admaif@702d0000 {
 119             compatible = "nvidia,tegra210-admaif";
 120             reg = <0x702d0000 0x800>;
 121             dmas = <&adma 1>,  <&adma 1>,
 122                    <&adma 2>,  <&adma 2>,
 123                    <&adma 3>,  <&adma 3>,
 124                    <&adma 4>,  <&adma 4>,
 125                    <&adma 5>,  <&adma 5>,
 126                    <&adma 6>,  <&adma 6>,
 127                    <&adma 7>,  <&adma 7>,
 128                    <&adma 8>,  <&adma 8>,
 129                    <&adma 9>,  <&adma 9>,
 130                    <&adma 10>, <&adma 10>;
 131             dma-names = "rx1",  "tx1",
 132                         "rx2",  "tx2",
 133                         "rx3",  "tx3",
 134                         "rx4",  "tx4",
 135                         "rx5",  "tx5",
 136                         "rx6",  "tx6",
 137                         "rx7",  "tx7",
 138                         "rx8",  "tx8",
 139                         "rx9",  "tx9",
 140                         "rx10", "tx10";
 141
 142             ports {
 143                 #address-cells = <1>;
 144                 #size-cells = <0>;
 145
 146                 admaif1_port: port@0 {
 147                     reg = <0x0>;
 148                     admaif1_ep: endpoint {
 149                         remote-endpoint = <&xbar_admaif1_ep>;
 150                     };
 151                 };
 152
 153                 // More ADMAIF ports to follow
 154             };
 155         };
 156
 157         i2s@702d1000 {
 158             compatible = "nvidia,tegra210-i2s";
 159             clocks = <&tegra_car TEGRA210_CLK_I2S0>;
 160             clock-names = "i2s";
 161             assigned-clocks = <&tegra_car TEGRA210_CLK_I2S0>;
 162             assigned-clock-parents = <&tegra_car TEGRA210_CLK_PLL_A_OUT0>;
 163             assigned-clock-rates = <1536000>;
 164             reg = <0x702d1000 0x100>;
 165
 166             ports {
 167                 #address-cells = <1>;
 168                 #size-cells = <0>;
 169
 170                 port@0 {
 171                     reg = <0x0>;
 172
 173                     i2s1_cif_ep: endpoint {
 174                         remote-endpoint = <&xbar_i2s1_ep>;
 175                     };
 176                 };
 177
 178                 i2s1_port: port@1 {
 179                     reg = <0x1>;
 180
 181                     i2s1_dap: endpoint {
 182                         dai-format = "i2s";
 183                     };
 184                 };
 185             };
 186         };
 187     };
 188
 189 ...