Documentation/devicetree/bindings/soc/qcom/qcom,geni-se.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/soc/qcom/qcom,geni-se.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: GENI Serial Engine QUP Wrapper Controller
   8
   9 maintainers:
  10   - Mukesh Savaliya <msavaliy@codeaurora.org>
  11   - Akash Asthana <akashast@codeaurora.org>
  12
  13 description: |
  14  Generic Interface (GENI) based Qualcomm Universal Peripheral (QUP) wrapper
  15  is a programmable module for supporting a wide range of serial interfaces
  16  like UART, SPI, I2C, I3C, etc. A single QUP module can provide upto 8 Serial
  17  Interfaces, using its internal Serial Engines. The GENI Serial Engine QUP
  18  Wrapper controller is modeled as a node with zero or more child nodes each
  19  representing a serial engine.
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - qcom,geni-se-qup
  25
  26   reg:
  27     description: QUP wrapper common register address and length.
  28     maxItems: 1
  29
  30   clock-names:
  31     items:
  32       - const: m-ahb
  33       - const: s-ahb
  34
  35   clocks:
  36     items:
  37       - description: Master AHB Clock
  38       - description: Slave AHB Clock
  39
  40   "#address-cells":
  41     const: 2
  42
  43   "#size-cells":
  44     const: 2
  45
  46   ranges: true
  47
  48   interconnects:
  49     maxItems: 1
  50
  51   interconnect-names:
  52     const: qup-core
  53
  54   iommus:
  55     maxItems: 1
  56
  57 required:
  58   - compatible
  59   - reg
  60   - clock-names
  61   - clocks
  62   - "#address-cells"
  63   - "#size-cells"
  64   - ranges
  65
  66 patternProperties:
  67   "^.*@[0-9a-f]+$":
  68     type: object
  69     description: Common properties for GENI Serial Engine based I2C, SPI and
  70                  UART controller.
  71
  72     properties:
  73       reg:
  74         description: GENI Serial Engine register address and length.
  75         maxItems: 1
  76
  77       clock-names:
  78         const: se
  79
  80       clocks:
  81         description: Serial engine core clock needed by the device.
  82         maxItems: 1
  83
  84       interconnects:
  85         minItems: 2
  86         maxItems: 3
  87
  88       interconnect-names:
  89         minItems: 2
  90         items:
  91           - const: qup-core
  92           - const: qup-config
  93           - const: qup-memory
  94
  95     required:
  96       - reg
  97       - clock-names
  98       - clocks
  99
 100   "spi@[0-9a-f]+$":
 101     type: object
 102     description: GENI serial engine based SPI controller. SPI in master mode
 103                  supports up to 50MHz, up to four chip selects, programmable
 104                  data path from 4 bits to 32 bits and numerous protocol
 105                  variants.
 106     $ref: /spi/spi-controller.yaml#
 107
 108     properties:
 109       compatible:
 110         enum:
 111           - qcom,geni-spi
 112
 113       interrupts:
 114         maxItems: 1
 115
 116       "#address-cells":
 117         const: 1
 118
 119       "#size-cells":
 120         const: 0
 121
 122     required:
 123       - compatible
 124       - interrupts
 125       - "#address-cells"
 126       - "#size-cells"
 127
 128   "i2c@[0-9a-f]+$":
 129     type: object
 130     description: GENI serial engine based I2C controller.
 131     $ref: /schemas/i2c/i2c-controller.yaml#
 132
 133     properties:
 134       compatible:
 135         enum:
 136           - qcom,geni-i2c
 137
 138       interrupts:
 139         maxItems: 1
 140
 141       "#address-cells":
 142         const: 1
 143
 144       "#size-cells":
 145         const: 0
 146
 147       clock-frequency:
 148         description: Desired I2C bus clock frequency in Hz.
 149         default: 100000
 150
 151     required:
 152       - compatible
 153       - interrupts
 154       - "#address-cells"
 155       - "#size-cells"
 156
 157   "serial@[0-9a-f]+$":
 158     type: object
 159     description: GENI Serial Engine based UART Controller.
 160     $ref: /schemas/serial.yaml#
 161
 162     properties:
 163       compatible:
 164         enum:
 165           - qcom,geni-uart
 166           - qcom,geni-debug-uart
 167
 168       interrupts:
 169         minItems: 1
 170         items:
 171           - description: UART core irq
 172           - description: Wakeup irq (RX GPIO)
 173
 174     required:
 175       - compatible
 176       - interrupts
 177
 178 additionalProperties: false
 179
 180 examples:
 181   - |
 182     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 183     #include <dt-bindings/interrupt-controller/arm-gic.h>
 184
 185     soc {
 186         #address-cells = <2>;
 187         #size-cells = <2>;
 188
 189         geniqup@8c0000 {
 190             compatible = "qcom,geni-se-qup";
 191             reg = <0 0x008c0000 0 0x6000>;
 192             clock-names = "m-ahb", "s-ahb";
 193             clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
 194                 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
 195             #address-cells = <2>;
 196             #size-cells = <2>;
 197             ranges;
 198
 199             i2c0: i2c@a94000 {
 200                 compatible = "qcom,geni-i2c";
 201                 reg = <0 0xa94000 0 0x4000>;
 202                 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>;
 203                 clock-names = "se";
 204                 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
 205                 pinctrl-names = "default", "sleep";
 206                 pinctrl-0 = <&qup_1_i2c_5_active>;
 207                 pinctrl-1 = <&qup_1_i2c_5_sleep>;
 208                 #address-cells = <1>;
 209                 #size-cells = <0>;
 210             };
 211
 212             uart0: serial@a88000 {
 213                 compatible = "qcom,geni-uart";
 214                 reg = <0 0xa88000 0 0x7000>;
 215                 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>;
 216                 clock-names = "se";
 217                 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
 218                 pinctrl-names = "default", "sleep";
 219                 pinctrl-0 = <&qup_1_uart_3_active>;
 220                 pinctrl-1 = <&qup_1_uart_3_sleep>;
 221             };
 222         };
 223     };
 224
 225 ...