1 # Copyright 2020 Lubomir Rintel <lkundrak@v3.sk>
4 $id: http://devicetree.org/schemas/serial/8250.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: UART (Universal Asynchronous Receiver/Transmitter) bindings
10 - devicetree@vger.kernel.org
19 - aspeed,lpc-interrupts
21 - aspeed,sirq-polarity-sense
25 const: aspeed,ast2500-vuart
48 - required: [ clock-frequency ]
49 - required: [ clocks ]
59 - const: aspeed,ast2400-vuart
60 - const: aspeed,ast2500-vuart
61 - const: intel,xscale-uart
62 - const: mrvl,pxa-uart
63 - const: nuvoton,wpcm450-uart
64 - const: nuvoton,npcm750-uart
65 - const: nvidia,tegra20-uart
66 - const: nxp,lpc3220-uart
82 - opencores,uart16550-rtlsvn105
88 - cavium,octeon-3860-uart
89 - xlnx,xps-uart16550-2.00.b
92 - ns16550 # Deprecated, unless the FIFO really is broken
99 - const: ralink,rt2880-uart
101 - ns16550 # Deprecated, unless the FIFO really is broken
105 - mediatek,mt7622-btif
106 - mediatek,mt7623-btif
107 - const: mediatek,mtk-btif
109 - const: mrvl,mmp-uart
110 - const: intel,xscale-uart
113 - nvidia,tegra30-uart
114 - nvidia,tegra114-uart
115 - nvidia,tegra124-uart
116 - nvidia,tegra186-uart
117 - nvidia,tegra194-uart
118 - nvidia,tegra210-uart
119 - const: nvidia,tegra20-uart
127 clock-frequency: true
136 $ref: /schemas/types.yaml#/definitions/uint32
137 description: The current active speed of the UART.
141 Offset to apply to the mapbase from the start of the registers.
144 description: Quantity to shift the register offsets by.
148 The size (in bytes) of the IO accesses that should be performed on the
149 device. There are some systems that require 32-bit accesses to the
150 UART (e.g. TI davinci).
155 Set to indicate that the port is in use by the OpenFirmware RTAS and
156 should not be registered.
161 Set to indicate that the port does not implement loopback test mode.
164 $ref: /schemas/types.yaml#/definitions/uint32
165 description: The fifo size of the UART.
170 One way to enable automatic flow control support. The driver is
171 allowed to detect support for the capability even without this
176 Specify the TX FIFO low water indication for parts with programmable
181 How long to pause uart rx when input overrun is encountered.
190 aspeed,sirq-polarity-sense:
191 $ref: /schemas/types.yaml#/definitions/phandle-array
193 Phandle to aspeed,ast2500-scu compatible syscon alongside register
194 offset and bit number to identify how the SIRQ polarity should be
195 configured. One possible data source is the LPC/eSPI mode bit. Only
196 applicable to aspeed,ast2500-vuart.
200 $ref: '/schemas/types.yaml#/definitions/uint32'
202 The VUART LPC address. Only applicable to aspeed,ast2500-vuart.
204 aspeed,lpc-interrupts:
205 $ref: "/schemas/types.yaml#/definitions/uint32-array"
209 A 2-cell property describing the VUART SIRQ number and SIRQ
210 polarity (IRQ_TYPE_LEVEL_LOW or IRQ_TYPE_LEVEL_HIGH). Only
211 applicable to aspeed,ast2500-vuart.
217 unevaluatedProperties: false
222 compatible = "ns8250";
223 reg = <0x80230000 0x100>;
226 clock-frequency = <48000000>;
229 #include <dt-bindings/gpio/gpio.h>
231 compatible = "andestech,uart16550", "ns16550a";
232 reg = <0x49042000 0x400>;
234 clock-frequency = <48000000>;
235 cts-gpios = <&gpio3 5 GPIO_ACTIVE_LOW>;
236 rts-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
237 dtr-gpios = <&gpio1 12 GPIO_ACTIVE_LOW>;
238 dsr-gpios = <&gpio1 13 GPIO_ACTIVE_LOW>;
239 dcd-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
240 rng-gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
243 #include <dt-bindings/clock/aspeed-clock.h>
244 #include <dt-bindings/interrupt-controller/irq.h>
246 compatible = "aspeed,ast2500-vuart";
247 reg = <0x1e787000 0x40>;
250 clocks = <&syscon ASPEED_CLK_APB>;
252 aspeed,lpc-io-reg = <0x3f8>;
253 aspeed,lpc-interrupts = <4 IRQ_TYPE_LEVEL_LOW>;