Documentation/devicetree/bindings/riscv/sifive-l2-cache.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 # Copyright (C) 2020 SiFive, Inc.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/riscv/sifive-l2-cache.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: SiFive L2 Cache Controller
   9
  10 maintainers:
  11   - Sagar Kadam <sagar.kadam@sifive.com>
  12   - Yash Shah <yash.shah@sifive.com>
  13   - Paul Walmsley  <paul.walmsley@sifive.com>
  14
  15 description:
  16   The SiFive Level 2 Cache Controller is used to provide access to fast copies
  17   of memory for masters in a Core Complex. The Level 2 Cache Controller also
  18   acts as directory-based coherency manager.
  19   All the properties in ePAPR/DeviceTree specification applies for this platform.
  20
  21 allOf:
  22   - $ref: /schemas/cache-controller.yaml#
  23
  24 select:
  25   properties:
  26     compatible:
  27       items:
  28         - enum:
  29             - sifive,fu540-c000-ccache
  30
  31   required:
  32     - compatible
  33
  34 properties:
  35   compatible:
  36     items:
  37       - const: sifive,fu540-c000-ccache
  38       - const: cache
  39
  40   cache-block-size:
  41     const: 64
  42
  43   cache-level:
  44     const: 2
  45
  46   cache-sets:
  47     const: 1024
  48
  49   cache-size:
  50     const: 2097152
  51
  52   cache-unified: true
  53
  54   interrupts:
  55     description: |
  56       Must contain entries for DirError, DataError and DataFail signals.
  57     minItems: 3
  58     maxItems: 3
  59
  60   reg:
  61     maxItems: 1
  62
  63   next-level-cache: true
  64
  65   memory-region:
  66     description: |
  67       The reference to the reserved-memory for the L2 Loosely Integrated Memory region.
  68       The reserved memory node should be defined as per the bindings in reserved-memory.txt.
  69
  70 additionalProperties: false
  71
  72 required:
  73   - compatible
  74   - cache-block-size
  75   - cache-level
  76   - cache-sets
  77   - cache-size
  78   - cache-unified
  79   - interrupts
  80   - reg
  81
  82 examples:
  83   - |
  84     cache-controller@2010000 {
  85         compatible = "sifive,fu540-c000-ccache", "cache";
  86         cache-block-size = <64>;
  87         cache-level = <2>;
  88         cache-sets = <1024>;
  89         cache-size = <2097152>;
  90         cache-unified;
  91         reg = <0x2010000 0x1000>;
  92         interrupt-parent = <&plic0>;
  93         interrupts = <1>,
  94                      <2>,
  95                      <3>;
  96         next-level-cache = <&L25>;
  97         memory-region = <&l2_lim>;
  98     };