Documentation/devicetree/bindings/power/rockchip,power-controller.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/power/rockchip,power-controller.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Rockchip Power Domains
   8
   9 maintainers:
  10   - Elaine Zhang <zhangqing@rock-chips.com>
  11   - Heiko Stuebner <heiko@sntech.de>
  12
  13 description: |
  14   Rockchip processors include support for multiple power domains
  15   which can be powered up/down by software based on different
  16   application scenarios to save power.
  17
  18   Power domains contained within power-controller node are
  19   generic power domain providers documented in
  20   Documentation/devicetree/bindings/power/power-domain.yaml.
  21
  22   IP cores belonging to a power domain should contain a
  23   "power-domains" property that is a phandle for the
  24   power domain node representing the domain.
  25
  26 properties:
  27   $nodename:
  28     const: power-controller
  29
  30   compatible:
  31     enum:
  32       - rockchip,px30-power-controller
  33       - rockchip,rk3036-power-controller
  34       - rockchip,rk3066-power-controller
  35       - rockchip,rk3128-power-controller
  36       - rockchip,rk3188-power-controller
  37       - rockchip,rk3228-power-controller
  38       - rockchip,rk3288-power-controller
  39       - rockchip,rk3328-power-controller
  40       - rockchip,rk3366-power-controller
  41       - rockchip,rk3368-power-controller
  42       - rockchip,rk3399-power-controller
  43       - rockchip,rk3568-power-controller
  44
  45   "#power-domain-cells":
  46     const: 1
  47
  48   "#address-cells":
  49     const: 1
  50
  51   "#size-cells":
  52     const: 0
  53
  54 required:
  55   - compatible
  56   - "#power-domain-cells"
  57
  58 additionalProperties: false
  59
  60 patternProperties:
  61   "^power-domain@[0-9a-f]+$":
  62
  63     $ref: "#/$defs/pd-node"
  64
  65     unevaluatedProperties: false
  66
  67     properties:
  68       "#address-cells":
  69         const: 1
  70
  71       "#size-cells":
  72         const: 0
  73
  74     patternProperties:
  75       "^power-domain@[0-9a-f]+$":
  76
  77         $ref: "#/$defs/pd-node"
  78
  79         unevaluatedProperties: false
  80
  81         properties:
  82           "#address-cells":
  83             const: 1
  84
  85           "#size-cells":
  86             const: 0
  87
  88         patternProperties:
  89           "^power-domain@[0-9a-f]+$":
  90
  91             $ref: "#/$defs/pd-node"
  92
  93             unevaluatedProperties: false
  94
  95             properties:
  96               "#power-domain-cells":
  97                 const: 0
  98
  99 $defs:
 100   pd-node:
 101     type: object
 102     description: |
 103       Represents the power domains within the power controller node.
 104
 105     properties:
 106       reg:
 107         maxItems: 1
 108         description: |
 109           Power domain index. Valid values are defined in
 110           "include/dt-bindings/power/px30-power.h"
 111           "include/dt-bindings/power/rk3036-power.h"
 112           "include/dt-bindings/power/rk3066-power.h"
 113           "include/dt-bindings/power/rk3128-power.h"
 114           "include/dt-bindings/power/rk3188-power.h"
 115           "include/dt-bindings/power/rk3228-power.h"
 116           "include/dt-bindings/power/rk3288-power.h"
 117           "include/dt-bindings/power/rk3328-power.h"
 118           "include/dt-bindings/power/rk3366-power.h"
 119           "include/dt-bindings/power/rk3368-power.h"
 120           "include/dt-bindings/power/rk3399-power.h"
 121           "include/dt-bindings/power/rk3568-power.h"
 122
 123       clocks:
 124         minItems: 1
 125         maxItems: 30
 126         description: |
 127           A number of phandles to clocks that need to be enabled
 128           while power domain switches state.
 129
 130       pm_qos:
 131         $ref: /schemas/types.yaml#/definitions/phandle-array
 132         description: |
 133           A number of phandles to qos blocks which need to be saved and restored
 134           while power domain switches state.
 135
 136       "#power-domain-cells":
 137         enum: [0, 1]
 138         description:
 139           Must be 0 for nodes representing a single PM domain and 1 for nodes
 140           providing multiple PM domains.
 141
 142     required:
 143       - reg
 144       - "#power-domain-cells"
 145
 146 examples:
 147   - |
 148     #include <dt-bindings/clock/rk3399-cru.h>
 149     #include <dt-bindings/power/rk3399-power.h>
 150
 151     soc {
 152         #address-cells = <2>;
 153         #size-cells = <2>;
 154
 155         qos_hdcp: qos@ffa90000 {
 156             compatible = "rockchip,rk3399-qos", "syscon";
 157             reg = <0x0 0xffa90000 0x0 0x20>;
 158         };
 159
 160         qos_iep: qos@ffa98000 {
 161             compatible = "rockchip,rk3399-qos", "syscon";
 162             reg = <0x0 0xffa98000 0x0 0x20>;
 163         };
 164
 165         qos_rga_r: qos@ffab0000 {
 166             compatible = "rockchip,rk3399-qos", "syscon";
 167             reg = <0x0 0xffab0000 0x0 0x20>;
 168         };
 169
 170         qos_rga_w: qos@ffab0080 {
 171             compatible = "rockchip,rk3399-qos", "syscon";
 172             reg = <0x0 0xffab0080 0x0 0x20>;
 173         };
 174
 175         qos_video_m0: qos@ffab8000 {
 176             compatible = "rockchip,rk3399-qos", "syscon";
 177             reg = <0x0 0xffab8000 0x0 0x20>;
 178         };
 179
 180         qos_video_m1_r: qos@ffac0000 {
 181             compatible = "rockchip,rk3399-qos", "syscon";
 182             reg = <0x0 0xffac0000 0x0 0x20>;
 183         };
 184
 185         qos_video_m1_w: qos@ffac0080 {
 186             compatible = "rockchip,rk3399-qos", "syscon";
 187             reg = <0x0 0xffac0080 0x0 0x20>;
 188         };
 189
 190         power-management@ff310000 {
 191             compatible = "rockchip,rk3399-pmu", "syscon", "simple-mfd";
 192             reg = <0x0 0xff310000 0x0 0x1000>;
 193
 194             power-controller {
 195                 compatible = "rockchip,rk3399-power-controller";
 196                 #power-domain-cells = <1>;
 197                 #address-cells = <1>;
 198                 #size-cells = <0>;
 199
 200                 /* These power domains are grouped by VD_CENTER */
 201                 power-domain@RK3399_PD_IEP {
 202                     reg = <RK3399_PD_IEP>;
 203                     clocks = <&cru ACLK_IEP>,
 204                              <&cru HCLK_IEP>;
 205                     pm_qos = <&qos_iep>;
 206                     #power-domain-cells = <0>;
 207                 };
 208                 power-domain@RK3399_PD_RGA {
 209                     reg = <RK3399_PD_RGA>;
 210                     clocks = <&cru ACLK_RGA>,
 211                              <&cru HCLK_RGA>;
 212                     pm_qos = <&qos_rga_r>,
 213                              <&qos_rga_w>;
 214                     #power-domain-cells = <0>;
 215                 };
 216                 power-domain@RK3399_PD_VCODEC {
 217                     reg = <RK3399_PD_VCODEC>;
 218                     clocks = <&cru ACLK_VCODEC>,
 219                              <&cru HCLK_VCODEC>;
 220                     pm_qos = <&qos_video_m0>;
 221                     #power-domain-cells = <0>;
 222                 };
 223                 power-domain@RK3399_PD_VDU {
 224                     reg = <RK3399_PD_VDU>;
 225                     clocks = <&cru ACLK_VDU>,
 226                              <&cru HCLK_VDU>;
 227                     pm_qos = <&qos_video_m1_r>,
 228                              <&qos_video_m1_w>;
 229                     #power-domain-cells = <0>;
 230                 };
 231                 power-domain@RK3399_PD_VIO {
 232                     reg = <RK3399_PD_VIO>;
 233                     #power-domain-cells = <1>;
 234                     #address-cells = <1>;
 235                     #size-cells = <0>;
 236
 237                     power-domain@RK3399_PD_HDCP {
 238                         reg = <RK3399_PD_HDCP>;
 239                         clocks = <&cru ACLK_HDCP>,
 240                                  <&cru HCLK_HDCP>,
 241                                  <&cru PCLK_HDCP>;
 242                         pm_qos = <&qos_hdcp>;
 243                         #power-domain-cells = <0>;
 244                     };
 245                 };
 246             };
 247         };
 248     };