Documentation/devicetree/bindings/power/reset/ocelot-reset.txt

   1 Microsemi Ocelot reset controller
   2
   3 The DEVCPU_GCB:CHIP_REGS have a SOFT_RST register that can be used to reset the
   4 SoC core.
   5
   6 The reset registers are both present in the MSCC vcoreiii MIPS and
   7 microchip Sparx5 armv8 SoC's.
   8
   9 Required Properties:
  10
  11  - compatible: "mscc,ocelot-chip-reset", "mscc,luton-chip-reset",
  12    "mscc,jaguar2-chip-reset" or "microchip,sparx5-chip-reset"
  13
  14 Example:
  15         reset@1070008 {
  16                 compatible = "mscc,ocelot-chip-reset";
  17                 reg = <0x1070008 0x4>;
  18         };
  19