1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/power/mediatek,power-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Mediatek Power Domains Controller
10 - Weiyi Lu <weiyi.lu@mediatek.com>
11 - Matthias Brugger <mbrugger@suse.com>
14 Mediatek processors include support for multiple power domains which can be
15 powered up/down by software based on different application scenes to save power.
17 IP cores belonging to a power domain should contain a 'power-domains'
18 property that is a phandle for SCPSYS node representing the domain.
22 const: power-controller
26 - mediatek,mt8173-power-controller
27 - mediatek,mt8183-power-controller
28 - mediatek,mt8192-power-controller
30 '#power-domain-cells':
40 "^power-domain@[0-9a-f]+$":
43 Represents the power domains within the power controller node as documented
44 in Documentation/devicetree/bindings/power/power-domain.yaml.
48 '#power-domain-cells':
50 Must be 0 for nodes representing a single PM domain and 1 for nodes
51 providing multiple PM domains.
61 Power domain index. Valid values are defined in:
62 "include/dt-bindings/power/mt8173-power.h" - for MT8173 type power domain.
63 "include/dt-bindings/power/mt8183-power.h" - for MT8183 type power domain.
64 "include/dt-bindings/power/mt8192-power.h" - for MT8192 type power domain.
69 A number of phandles to clocks that need to be enabled during domain
74 List of names of clocks, in order to match the power-up sequencing
75 for each power domain we need to group the clocks by name. BASIC
76 clocks need to be enabled before enabling the corresponding power
77 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
78 SUSBYS clocks need to be enabled before releasing the bus protection,
79 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
81 In order to follow properly the power-up sequencing, the clocks must
82 be specified by order, adding first the BASIC clocks followed by the
86 $ref: /schemas/types.yaml#/definitions/phandle
87 description: phandle to the device containing the INFRACFG register range.
90 $ref: /schemas/types.yaml#/definitions/phandle
91 description: phandle to the device containing the SMI register range.
94 "^power-domain@[0-9a-f]+$":
97 Represents a power domain child within a power domain parent node.
101 '#power-domain-cells':
103 Must be 0 for nodes representing a single PM domain and 1 for nodes
104 providing multiple PM domains.
117 A number of phandles to clocks that need to be enabled during domain
122 List of names of clocks, in order to match the power-up sequencing
123 for each power domain we need to group the clocks by name. BASIC
124 clocks need to be enabled before enabling the corresponding power
125 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
126 SUSBYS clocks need to be enabled before releasing the bus protection,
127 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
129 In order to follow properly the power-up sequencing, the clocks must
130 be specified by order, adding first the BASIC clocks followed by the
134 $ref: /schemas/types.yaml#/definitions/phandle
135 description: phandle to the device containing the INFRACFG register range.
138 $ref: /schemas/types.yaml#/definitions/phandle
139 description: phandle to the device containing the SMI register range.
142 "^power-domain@[0-9a-f]+$":
145 Represents a power domain child within a power domain parent node.
149 '#power-domain-cells':
151 Must be 0 for nodes representing a single PM domain and 1 for nodes
152 providing multiple PM domains.
165 A number of phandles to clocks that need to be enabled during domain
170 List of names of clocks, in order to match the power-up sequencing
171 for each power domain we need to group the clocks by name. BASIC
172 clocks need to be enabled before enabling the corresponding power
173 domain, and should not have a '-' in their name (i.e mm, mfg, venc).
174 SUSBYS clocks need to be enabled before releasing the bus protection,
175 and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
177 In order to follow properly the power-up sequencing, the clocks must
178 be specified by order, adding first the BASIC clocks followed by the
182 $ref: /schemas/types.yaml#/definitions/phandle
183 description: phandle to the device containing the INFRACFG register range.
186 $ref: /schemas/types.yaml#/definitions/phandle
187 description: phandle to the device containing the SMI register range.
192 additionalProperties: false
197 additionalProperties: false
202 additionalProperties: false
207 additionalProperties: false
211 #include <dt-bindings/clock/mt8173-clk.h>
212 #include <dt-bindings/power/mt8173-power.h>
215 #address-cells = <2>;
218 scpsys: syscon@10006000 {
219 compatible = "syscon", "simple-mfd";
220 reg = <0 0x10006000 0 0x1000>;
222 spm: power-controller {
223 compatible = "mediatek,mt8173-power-controller";
224 #address-cells = <1>;
226 #power-domain-cells = <1>;
228 /* power domains of the SoC */
229 power-domain@MT8173_POWER_DOMAIN_VDEC {
230 reg = <MT8173_POWER_DOMAIN_VDEC>;
231 clocks = <&topckgen CLK_TOP_MM_SEL>;
233 #power-domain-cells = <0>;
235 power-domain@MT8173_POWER_DOMAIN_VENC {
236 reg = <MT8173_POWER_DOMAIN_VENC>;
237 clocks = <&topckgen CLK_TOP_MM_SEL>,
238 <&topckgen CLK_TOP_VENC_SEL>;
239 clock-names = "mm", "venc";
240 #power-domain-cells = <0>;
242 power-domain@MT8173_POWER_DOMAIN_ISP {
243 reg = <MT8173_POWER_DOMAIN_ISP>;
244 clocks = <&topckgen CLK_TOP_MM_SEL>;
246 #power-domain-cells = <0>;
248 power-domain@MT8173_POWER_DOMAIN_MM {
249 reg = <MT8173_POWER_DOMAIN_MM>;
250 clocks = <&topckgen CLK_TOP_MM_SEL>;
252 #power-domain-cells = <0>;
253 mediatek,infracfg = <&infracfg>;
255 power-domain@MT8173_POWER_DOMAIN_VENC_LT {
256 reg = <MT8173_POWER_DOMAIN_VENC_LT>;
257 clocks = <&topckgen CLK_TOP_MM_SEL>,
258 <&topckgen CLK_TOP_VENC_LT_SEL>;
259 clock-names = "mm", "venclt";
260 #power-domain-cells = <0>;
262 power-domain@MT8173_POWER_DOMAIN_AUDIO {
263 reg = <MT8173_POWER_DOMAIN_AUDIO>;
264 #power-domain-cells = <0>;
266 power-domain@MT8173_POWER_DOMAIN_USB {
267 reg = <MT8173_POWER_DOMAIN_USB>;
268 #power-domain-cells = <0>;
270 power-domain@MT8173_POWER_DOMAIN_MFG_ASYNC {
271 reg = <MT8173_POWER_DOMAIN_MFG_ASYNC>;
274 #address-cells = <1>;
276 #power-domain-cells = <1>;
278 power-domain@MT8173_POWER_DOMAIN_MFG_2D {
279 reg = <MT8173_POWER_DOMAIN_MFG_2D>;
280 #address-cells = <1>;
282 #power-domain-cells = <1>;
284 power-domain@MT8173_POWER_DOMAIN_MFG {
285 reg = <MT8173_POWER_DOMAIN_MFG>;
286 #power-domain-cells = <0>;
287 mediatek,infracfg = <&infracfg>;