Documentation/devicetree/bindings/pinctrl/toshiba,visconti-pinctrl.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/toshiba,visconti-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Toshiba Visconti TMPV770x pin mux/config controller
   8
   9 maintainers:
  10   - Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
  11
  12 description:
  13   Toshiba's Visconti ARM SoC a pin mux/config controller.
  14
  15 properties:
  16   compatible:
  17     enum:
  18       - toshiba,tmpv7708-pinctrl
  19
  20   reg:
  21     maxItems: 1
  22
  23 required:
  24   - compatible
  25   - reg
  26
  27 patternProperties:
  28   '-pins$':
  29     type: object
  30     description: |
  31       A pinctrl node should contain at least one subnodes representing the
  32       pinctrl groups available on the machine. Each subnode will list the
  33       pins it needs, and how they should be configured, with regard to muxer
  34       configuration, pullups, drive strength.
  35     $ref: "pinmux-node.yaml"
  36
  37     properties:
  38       function:
  39         description:
  40           Function to mux.
  41         $ref: "/schemas/types.yaml#/definitions/string"
  42         enum: [i2c0, i2c1, i2c2, i2c3, i2c4, i2c5, i2c6, i2c7, i2c8,
  43                spi0, spi1, spi2, spi3, spi4, spi5, spi6,
  44                uart0, uart1, uart2, uart3, pwm, pcmif_out, pcmif_in]
  45
  46       groups:
  47         description:
  48           Name of the pin group to use for the functions.
  49         $ref: "/schemas/types.yaml#/definitions/string"
  50         enum: [i2c0_grp, i2c1_grp, i2c2_grp, i2c3_grp, i2c4_grp,
  51                i2c5_grp, i2c6_grp, i2c7_grp, i2c8_grp,
  52                spi0_grp, spi0_cs0_grp, spi0_cs1_grp, spi0_cs2_grp,
  53                spi1_grp, spi2_grp, spi3_grp, spi4_grp, spi5_grp, spi6_grp,
  54                uart0_grp, uart1_grp, uart2_grp, uart3_grp,
  55                pwm0_gpio4_grp, pwm0_gpio8_grp, pwm0_gpio12_grp,
  56                pwm0_gpio16_grp, pwm1_gpio5_grp, pwm1_gpio9_grp,
  57                pwm1_gpio13_grp, pwm1_gpio17_grp, pwm2_gpio6_grp,
  58                pwm2_gpio10_grp, pwm2_gpio14_grp, pwm2_gpio18_grp,
  59                pwm3_gpio7_grp, pwm3_gpio11_grp, pwm3_gpio15_grp,
  60                pwm3_gpio19_grp, pcmif_out_grp, pcmif_in_grp]
  61
  62       drive-strength:
  63         enum: [2, 4, 6, 8, 16, 24, 32]
  64         default: 2
  65         description:
  66           Selects the drive strength for the specified pins, in mA.
  67
  68       bias-pull-up: true
  69
  70       bias-pull-down: true
  71
  72       bias-disable: true
  73
  74 additionalProperties: false
  75
  76 examples:
  77   # Pinmux controller node
  78   - |
  79     soc {
  80         #address-cells = <2>;
  81         #size-cells = <2>;
  82
  83         pmux: pmux@24190000 {
  84             compatible = "toshiba,tmpv7708-pinctrl";
  85             reg = <0 0x24190000 0 0x10000>;
  86
  87             spi0_pins: spi0-pins {
  88                 function = "spi0";
  89                 groups = "spi0_grp";
  90             };
  91         };
  92     };