Documentation/devicetree/bindings/pinctrl/renesas,rzg2l-pinctrl.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas RZ/G2L combined Pin and GPIO controller
   8
   9 maintainers:
  10   - Geert Uytterhoeven <geert+renesas@glider.be>
  11   - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
  12
  13 description:
  14   The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
  15   controller.
  16   Pin multiplexing and GPIO configuration is performed on a per-pin basis.
  17   Each port features up to 8 pins, each of them configurable for GPIO function
  18   (port mode) or in alternate function mode.
  19   Up to 8 different alternate function modes exist for each single pin.
  20
  21 properties:
  22   compatible:
  23     enum:
  24       - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
  25
  26   reg:
  27     maxItems: 1
  28
  29   gpio-controller: true
  30
  31   '#gpio-cells':
  32     const: 2
  33     description:
  34       The first cell contains the global GPIO port index, constructed using the
  35       RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
  36       second cell represents consumer flag as mentioned in ../gpio/gpio.txt
  37       E.g. "RZG2L_GPIO(39, 1)" for P39_1.
  38
  39   gpio-ranges:
  40     maxItems: 1
  41
  42   clocks:
  43     maxItems: 1
  44
  45   power-domains:
  46     maxItems: 1
  47
  48   resets:
  49     items:
  50       - description: GPIO_RSTN signal
  51       - description: GPIO_PORT_RESETN signal
  52       - description: GPIO_SPARE_RESETN signal
  53
  54 additionalProperties:
  55   anyOf:
  56     - type: object
  57       allOf:
  58         - $ref: pincfg-node.yaml#
  59         - $ref: pinmux-node.yaml#
  60
  61       description:
  62         Pin controller client devices use pin configuration subnodes (children
  63         and grandchildren) for desired pin configuration.
  64         Client device subnodes use below standard properties.
  65
  66       properties:
  67         phandle: true
  68         pinmux:
  69           description:
  70             Values are constructed from GPIO port number, pin number, and
  71             alternate function configuration number using the RZG2L_PORT_PINMUX()
  72             helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
  73         pins: true
  74         drive-strength:
  75           enum: [ 2, 4, 8, 12 ]
  76         power-source:
  77           enum: [ 1800, 2500, 3300 ]
  78         slew-rate: true
  79         gpio-hog: true
  80         gpios: true
  81         input-enable: true
  82         output-high: true
  83         output-low: true
  84         line-name: true
  85
  86     - type: object
  87       properties:
  88         phandle: true
  89
  90       additionalProperties:
  91         $ref: "#/additionalProperties/anyOf/0"
  92
  93 required:
  94   - compatible
  95   - reg
  96   - gpio-controller
  97   - '#gpio-cells'
  98   - gpio-ranges
  99   - clocks
 100   - power-domains
 101   - resets
 102
 103 examples:
 104   - |
 105     #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
 106     #include <dt-bindings/clock/r9a07g044-cpg.h>
 107
 108     pinctrl: pinctrl@11030000 {
 109             compatible = "renesas,r9a07g044-pinctrl";
 110             reg = <0x11030000 0x10000>;
 111
 112             gpio-controller;
 113             #gpio-cells = <2>;
 114             gpio-ranges = <&pinctrl 0 0 392>;
 115             clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
 116             resets = <&cpg R9A07G044_GPIO_RSTN>,
 117                      <&cpg R9A07G044_GPIO_PORT_RESETN>,
 118                      <&cpg R9A07G044_GPIO_SPARE_RESETN>;
 119             power-domains = <&cpg>;
 120
 121             scif0_pins: serial0 {
 122                     pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
 123                              <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
 124             };
 125
 126             i2c1_pins: i2c1 {
 127                     pins = "RIIC1_SDA", "RIIC1_SCL";
 128                     input-enable;
 129             };
 130
 131             sd1-pwr-en-hog {
 132                     gpio-hog;
 133                     gpios = <RZG2L_GPIO(39, 2) 0>;
 134                     output-high;
 135                     line-name = "sd1_pwr_en";
 136             };
 137
 138             sdhi1_pins: sd1 {
 139                     sd1_mux {
 140                             pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
 141                                      <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
 142                             power-source  = <3300>;
 143                     };
 144
 145                     sd1_data {
 146                             pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
 147                             power-source  = <3300>;
 148                     };
 149
 150                     sd1_ctrl {
 151                             pins = "SD1_CLK", "SD1_CMD";
 152                             power-source  = <3300>;
 153                     };
 154             };
 155     };