1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/renesas,rzg2l-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas RZ/G2L combined Pin and GPIO controller
10 - Geert Uytterhoeven <geert+renesas@glider.be>
11 - Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
14 The Renesas SoCs of the RZ/G2L series feature a combined Pin and GPIO
16 Pin multiplexing and GPIO configuration is performed on a per-pin basis.
17 Each port features up to 8 pins, each of them configurable for GPIO function
18 (port mode) or in alternate function mode.
19 Up to 8 different alternate function modes exist for each single pin.
24 - renesas,r9a07g044-pinctrl # RZ/G2{L,LC}
34 The first cell contains the global GPIO port index, constructed using the
35 RZG2L_GPIO() helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h> and the
36 second cell represents consumer flag as mentioned in ../gpio/gpio.txt
37 E.g. "RZG2L_GPIO(39, 1)" for P39_1.
50 - description: GPIO_RSTN signal
51 - description: GPIO_PORT_RESETN signal
52 - description: GPIO_SPARE_RESETN signal
58 - $ref: pincfg-node.yaml#
59 - $ref: pinmux-node.yaml#
62 Pin controller client devices use pin configuration subnodes (children
63 and grandchildren) for desired pin configuration.
64 Client device subnodes use below standard properties.
70 Values are constructed from GPIO port number, pin number, and
71 alternate function configuration number using the RZG2L_PORT_PINMUX()
72 helper macro in <dt-bindings/pinctrl/rzg2l-pinctrl.h>.
77 enum: [ 1800, 2500, 3300 ]
91 $ref: "#/additionalProperties/anyOf/0"
105 #include <dt-bindings/pinctrl/rzg2l-pinctrl.h>
106 #include <dt-bindings/clock/r9a07g044-cpg.h>
108 pinctrl: pinctrl@11030000 {
109 compatible = "renesas,r9a07g044-pinctrl";
110 reg = <0x11030000 0x10000>;
114 gpio-ranges = <&pinctrl 0 0 392>;
115 clocks = <&cpg CPG_MOD R9A07G044_GPIO_HCLK>;
116 resets = <&cpg R9A07G044_GPIO_RSTN>,
117 <&cpg R9A07G044_GPIO_PORT_RESETN>,
118 <&cpg R9A07G044_GPIO_SPARE_RESETN>;
119 power-domains = <&cpg>;
121 scif0_pins: serial0 {
122 pinmux = <RZG2L_PORT_PINMUX(38, 0, 1)>, /* Tx */
123 <RZG2L_PORT_PINMUX(38, 1, 1)>; /* Rx */
127 pins = "RIIC1_SDA", "RIIC1_SCL";
133 gpios = <RZG2L_GPIO(39, 2) 0>;
135 line-name = "sd1_pwr_en";
140 pinmux = <RZG2L_PORT_PINMUX(19, 0, 1)>, /* CD */
141 <RZG2L_PORT_PINMUX(19, 1, 1)>; /* WP */
142 power-source = <3300>;
146 pins = "SD1_DATA0", "SD1_DATA1", "SD1_DATA2", "SD1_DATA3";
147 power-source = <3300>;
151 pins = "SD1_CLK", "SD1_CMD";
152 power-source = <3300>;