1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/pinctrl/qcom,sm6115-pinctrl.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Qualcomm Technologies, Inc. SM6115, SM4250 TLMM block
10 - Iskren Chernev <iskren.chernev@gmail.com>
13 This binding describes the Top Level Mode Multiplexer block found in the
14 SM4250/6115 platforms.
18 const: qcom,sm6115-tlmm
31 description: Specifies the TLMM summary IRQ
34 interrupt-controller: true
38 Specifies the PIN numbers and Flags, as defined in defined in
39 include/dt-bindings/interrupt-controller/irq.h
45 description: Specifying the pin number and flags, as defined in
46 include/dt-bindings/gpio/gpio.h
55 #PIN CONFIGURATION NODES
59 - $ref: "#/$defs/qcom-sm6115-tlmm-state"
62 $ref: "#/$defs/qcom-sm6115-tlmm-state"
65 qcom-sm6115-tlmm-state:
68 Pinctrl node's client devices use subnodes for desired pin configuration.
69 Client device subnodes use below standard properties.
70 $ref: "qcom,tlmm-common.yaml#/$defs/qcom-tlmm-state"
75 List of gpio pins affected by the properties specified in this
79 - pattern: "^gpio([0-9]|[1-9][0-9]|10[0-9]|11[0-2])$"
80 - enum: [ sdc1_rclk, sdc1_clk, sdc1_cmd, sdc1_data,
81 sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset ]
87 Specify the alternative function to be configured for the specified
90 enum: [ adsp_ext, agera_pll, atest, cam_mclk, cci_async, cci_i2c,
91 cci_timer, cri_trng, dac_calib, dbg_out, ddr_bist, ddr_pxi0,
92 ddr_pxi1, ddr_pxi2, ddr_pxi3, gcc_gp1, gcc_gp2, gcc_gp3, gpio,
93 gp_pdm0, gp_pdm1, gp_pdm2, gsm0_tx, gsm1_tx, jitter_bist,
94 mdp_vsync, mdp_vsync_out_0, mdp_vsync_out_1, mpm_pwr, mss_lte,
95 m_voc, nav_gpio, pa_indicator, pbs, pbs_out, phase_flag,
96 pll_bist, pll_bypassnl, pll_reset, prng_rosc, qdss_cti,
97 qdss_gpio, qup0, qup1, qup2, qup3, qup4, qup5, sdc1_tb,
98 sdc2_tb, sd_write, ssbi_wtr1, tgu, tsense_pwm, uim1_clk,
99 uim1_data, uim1_present, uim1_reset, uim2_clk, uim2_data,
100 uim2_present, uim2_reset, usb_phy, vfr_1, vsense_trigger,
101 wlan1_adc0, elan1_adc1 ]
104 enum: [2, 4, 6, 8, 10, 12, 14, 16]
107 Selects the drive strength for the specified pins, in mA.
122 additionalProperties: false
129 - interrupt-controller
135 additionalProperties: false
139 #include <dt-bindings/interrupt-controller/arm-gic.h>
140 tlmm: pinctrl@500000 {
141 compatible = "qcom,sm6115-tlmm";
142 reg = <0x500000 0x400000>,
145 reg-names = "west", "south", "east";
146 interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
149 interrupt-controller;
150 #interrupt-cells = <2>;
151 gpio-ranges = <&tlmm 0 0 114>;
153 sdc2_on_state: sdc2-on-state {
157 drive-strength = <16>;
163 drive-strength = <10>;
169 drive-strength = <10>;
176 drive-strength = <2>;