Documentation/devicetree/bindings/pinctrl/pinctrl-mt65xx.txt

   1 * Mediatek MT65XX Pin Controller
   2
   3 The Mediatek's Pin controller is used to control SoC pins.
   4
   5 Required properties:
   6 - compatible: value should be one of the following.
   7         "mediatek,mt2701-pinctrl", compatible with mt2701 pinctrl.
   8         "mediatek,mt2712-pinctrl", compatible with mt2712 pinctrl.
   9         "mediatek,mt6397-pinctrl", compatible with mt6397 pinctrl.
  10         "mediatek,mt7623-pinctrl", compatible with mt7623 pinctrl.
  11         "mediatek,mt8127-pinctrl", compatible with mt8127 pinctrl.
  12         "mediatek,mt8135-pinctrl", compatible with mt8135 pinctrl.
  13         "mediatek,mt8167-pinctrl", compatible with mt8167 pinctrl.
  14         "mediatek,mt8173-pinctrl", compatible with mt8173 pinctrl.
  15         "mediatek,mt8365-pinctrl", compatible with mt8365 pinctrl.
  16         "mediatek,mt8516-pinctrl", compatible with mt8516 pinctrl.
  17 - pins-are-numbered: Specify the subnodes are using numbered pinmux to
  18   specify pins.
  19 - gpio-controller : Marks the device node as a gpio controller.
  20 - #gpio-cells: number of cells in GPIO specifier. Since the generic GPIO
  21   binding is used, the amount of cells must be specified as 2. See the below
  22   mentioned gpio binding representation for description of particular cells.
  23
  24         Eg: <&pio 6 0>
  25         <[phandle of the gpio controller node]
  26         [line number within the gpio controller]
  27         [flags]>
  28
  29         Values for gpio specifier:
  30         - Line number: is a value between 0 to 202.
  31         - Flags:  bit field of flags, as defined in <dt-bindings/gpio/gpio.h>.
  32             Only the following flags are supported:
  33             0 - GPIO_ACTIVE_HIGH
  34             1 - GPIO_ACTIVE_LOW
  35
  36 Optional properties:
  37 - mediatek,pctl-regmap: Should be a phandle of the syscfg node.
  38 - reg: physicall address base for EINT registers
  39 - interrupt-controller: Marks the device node as an interrupt controller
  40 - #interrupt-cells: Should be two.
  41 - interrupts : The interrupt outputs from the controller.
  42
  43 Please refer to pinctrl-bindings.txt in this directory for details of the
  44 common pinctrl bindings used by client devices.
  45
  46 Subnode format
  47 A pinctrl node should contain at least one subnodes representing the
  48 pinctrl groups available on the machine. Each subnode will list the
  49 pins it needs, and how they should be configured, with regard to muxer
  50 configuration, pullups, drive strength, input enable/disable and input schmitt.
  51
  52     node {
  53         pinmux = <PIN_NUMBER_PINMUX>;
  54         GENERIC_PINCONFIG;
  55     };
  56
  57 Required properties:
  58 - pinmux: integer array, represents gpio pin number and mux setting.
  59     Supported pin number and mux varies for different SoCs, and are defined
  60     as macros in boot/dts/<soc>-pinfunc.h directly.
  61
  62 Optional properties:
  63 - GENERIC_PINCONFIG: is the generic pinconfig options to use, bias-disable,
  64     bias-pull-down, bias-pull-up, input-enable, input-disable, output-low, output-high,
  65     input-schmitt-enable, input-schmitt-disable and drive-strength are valid.
  66
  67     Some special pins have extra pull up strength, there are R0 and R1 pull-up
  68     resistors available, but for user, it's only need to set R1R0 as 00, 01, 10 or 11.
  69     So when config bias-pull-up, it support arguments for those special pins.
  70     Some macros have been defined for this usage, such as MTK_PUPD_SET_R1R0_00.
  71     See dt-bindings/pinctrl/mt65xx.h.
  72
  73     When config drive-strength, it can support some arguments, such as
  74     MTK_DRIVE_4mA, MTK_DRIVE_6mA, etc. See dt-bindings/pinctrl/mt65xx.h.
  75
  76 Examples:
  77
  78 #include "mt8135-pinfunc.h"
  79
  80 ...
  81 {
  82         syscfg_pctl_a: syscfg-pctl-a@10005000 {
  83                 compatible = "mediatek,mt8135-pctl-a-syscfg", "syscon";
  84                 reg = <0 0x10005000 0 0x1000>;
  85         };
  86
  87         syscfg_pctl_b: syscfg-pctl-b@1020c020 {
  88                 compatible = "mediatek,mt8135-pctl-b-syscfg", "syscon";
  89                 reg = <0 0x1020C020 0 0x1000>;
  90         };
  91
  92         pinctrl@1c20800 {
  93                 compatible = "mediatek,mt8135-pinctrl";
  94                 reg = <0 0x1000B000 0 0x1000>;
  95                 mediatek,pctl-regmap = <&syscfg_pctl_a>, <&syscfg_pctl_b>;
  96                 pins-are-numbered;
  97                 gpio-controller;
  98                 #gpio-cells = <2>;
  99                 interrupt-controller;
 100                 #interrupt-cells = <2>;
 101                 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
 102                                 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
 103                                 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
 104
 105                 i2c0_pins_a: i2c0@0 {
 106                         pins1 {
 107                                 pinmux = <MT8135_PIN_100_SDA0__FUNC_SDA0>,
 108                                          <MT8135_PIN_101_SCL0__FUNC_SCL0>;
 109                                 bias-disable;
 110                         };
 111                 };
 112
 113                 i2c1_pins_a: i2c1@0 {
 114                         pins {
 115                                 pinmux = <MT8135_PIN_195_SDA1__FUNC_SDA1>,
 116                                          <MT8135_PIN_196_SCL1__FUNC_SCL1>;
 117                                 bias-pull-up = <55>;
 118                         };
 119                 };
 120
 121                 i2c2_pins_a: i2c2@0 {
 122                         pins1 {
 123                                 pinmux = <MT8135_PIN_193_SDA2__FUNC_SDA2>;
 124                                 bias-pull-down;
 125                         };
 126
 127                         pins2 {
 128                                 pinmux = <MT8135_PIN_49_WATCHDOG__FUNC_GPIO49>;
 129                                 bias-pull-up;
 130                         };
 131                 };
 132
 133                 i2c3_pins_a: i2c3@0 {
 134                         pins1 {
 135                                 pinmux = <MT8135_PIN_40_DAC_CLK__FUNC_GPIO40>,
 136                                          <MT8135_PIN_41_DAC_WS__FUNC_GPIO41>;
 137                                 bias-pull-up = <55>;
 138                         };
 139
 140                         pins2 {
 141                                 pinmux = <MT8135_PIN_35_SCL3__FUNC_SCL3>,
 142                                          <MT8135_PIN_36_SDA3__FUNC_SDA3>;
 143                                 output-low;
 144                                 bias-pull-up = <55>;
 145                         };
 146
 147                         pins3 {
 148                                 pinmux = <MT8135_PIN_57_JTCK__FUNC_GPIO57>,
 149                                          <MT8135_PIN_60_JTDI__FUNC_JTDI>;
 150                                 drive-strength = <32>;
 151                         };
 152                 };
 153
 154                 ...
 155         }
 156 };