Documentation/devicetree/bindings/phy/renesas,usb2-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/renesas,usb2-phy.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Renesas R-Car generation 3 USB 2.0 PHY
   8
   9 maintainers:
  10   - Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
  11
  12 properties:
  13   compatible:
  14     oneOf:
  15       - items:
  16           - const: renesas,usb2-phy-r8a77470 # RZ/G1C
  17
  18       - items:
  19           - enum:
  20               - renesas,usb2-phy-r7s9210  # RZ/A2
  21               - renesas,usb2-phy-r8a774a1 # RZ/G2M
  22               - renesas,usb2-phy-r8a774b1 # RZ/G2N
  23               - renesas,usb2-phy-r8a774c0 # RZ/G2E
  24               - renesas,usb2-phy-r8a774e1 # RZ/G2H
  25               - renesas,usb2-phy-r8a7795  # R-Car H3
  26               - renesas,usb2-phy-r8a7796  # R-Car M3-W
  27               - renesas,usb2-phy-r8a77961 # R-Car M3-W+
  28               - renesas,usb2-phy-r8a77965 # R-Car M3-N
  29               - renesas,usb2-phy-r8a77990 # R-Car E3
  30               - renesas,usb2-phy-r8a77995 # R-Car D3
  31           - const: renesas,rcar-gen3-usb2-phy
  32
  33       - items:
  34           - enum:
  35               - renesas,usb2-phy-r9a07g044 # RZ/G2{L,LC}
  36           - const: renesas,rzg2l-usb2-phy  # RZ/G2L family
  37
  38   reg:
  39     maxItems: 1
  40
  41   clocks:
  42     minItems: 1
  43     maxItems: 2
  44
  45   clock-names:
  46     minItems: 1
  47     items:
  48       - const: fck
  49       - const: usb_x1
  50
  51   '#phy-cells':
  52     enum: [0, 1]  # and 0 is deprecated.
  53     description: |
  54       The phandle's argument in the PHY specifier is the INT_STATUS bit of
  55       controller.
  56       - 1 = USBH_INTA (OHCI)
  57       - 2 = USBH_INTB (EHCI)
  58       - 3 = UCOM_INT (OTG and BC)
  59
  60   interrupts:
  61     maxItems: 1
  62
  63   power-domains:
  64     maxItems: 1
  65
  66   resets:
  67     minItems: 1
  68     items:
  69       - description: reset of USB 2.0 host side
  70       - description: reset of USB 2.0 peripheral side
  71
  72   vbus-supply:
  73     description: |
  74       Phandle to a regulator that provides power to the VBUS. This regulator
  75       will be managed during the PHY power on/off sequence.
  76
  77   renesas,no-otg-pins:
  78     $ref: /schemas/types.yaml#/definitions/flag
  79     description: |
  80       specify when a board does not provide proper otg pins.
  81
  82   dr_mode: true
  83
  84 if:
  85   properties:
  86     compatible:
  87       contains:
  88         const: renesas,usb2-phy-r7s9210
  89 then:
  90   required:
  91     - clock-names
  92
  93 required:
  94   - compatible
  95   - reg
  96   - clocks
  97   - '#phy-cells'
  98
  99 allOf:
 100   - if:
 101       properties:
 102         compatible:
 103           contains:
 104             const: renesas,rzg2l-usb2-phy
 105     then:
 106       required:
 107         - resets
 108
 109 additionalProperties: false
 110
 111 examples:
 112   - |
 113     #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
 114     #include <dt-bindings/interrupt-controller/arm-gic.h>
 115     #include <dt-bindings/power/r8a7795-sysc.h>
 116
 117     usb-phy@ee080200 {
 118         compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
 119         reg = <0xee080200 0x700>;
 120         interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>;
 121         clocks = <&cpg CPG_MOD 703>;
 122         #phy-cells = <1>;
 123     };
 124
 125     usb-phy@ee0a0200 {
 126         compatible = "renesas,usb2-phy-r8a7795", "renesas,rcar-gen3-usb2-phy";
 127         reg = <0xee0a0200 0x700>;
 128         clocks = <&cpg CPG_MOD 702>;
 129         #phy-cells = <1>;
 130     };