Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: Qualcomm QMP USB3 DP PHY controller
   9
  10 maintainers:
  11   - Manu Gautam <mgautam@codeaurora.org>
  12
  13 properties:
  14   compatible:
  15     enum:
  16       - qcom,sc7180-qmp-usb3-dp-phy
  17       - qcom,sc7280-qmp-usb3-dp-phy
  18       - qcom,sc8180x-qmp-usb3-dp-phy
  19       - qcom,sdm845-qmp-usb3-dp-phy
  20       - qcom,sm8250-qmp-usb3-dp-phy
  21   reg:
  22     items:
  23       - description: Address and length of PHY's USB serdes block.
  24       - description: Address and length of the DP_COM control block.
  25       - description: Address and length of PHY's DP serdes block.
  26
  27   reg-names:
  28     items:
  29       - const: usb
  30       - const: dp_com
  31       - const: dp
  32
  33   "#clock-cells":
  34     enum: [ 1, 2 ]
  35
  36   "#address-cells":
  37     enum: [ 1, 2 ]
  38
  39   "#size-cells":
  40     enum: [ 1, 2 ]
  41
  42   ranges: true
  43
  44   clocks:
  45     items:
  46       - description: Phy aux clock.
  47       - description: Phy config clock.
  48       - description: 19.2 MHz ref clk.
  49       - description: Phy common block aux clock.
  50
  51   clock-names:
  52     items:
  53       - const: aux
  54       - const: cfg_ahb
  55       - const: ref
  56       - const: com_aux
  57
  58   resets:
  59     items:
  60       - description: reset of phy block.
  61       - description: phy common block reset.
  62
  63   reset-names:
  64     items:
  65       - const: phy
  66       - const: common
  67
  68   vdda-phy-supply:
  69     description:
  70       Phandle to a regulator supply to PHY core block.
  71
  72   vdda-pll-supply:
  73     description:
  74       Phandle to 1.8V regulator supply to PHY refclk pll block.
  75
  76   vddp-ref-clk-supply:
  77     description:
  78       Phandle to a regulator supply to any specific refclk pll block.
  79
  80 #Required nodes:
  81 patternProperties:
  82   "^usb3-phy@[0-9a-f]+$":
  83     type: object
  84     description:
  85       The USB3 PHY.
  86
  87     properties:
  88       reg:
  89         items:
  90           - description: Address and length of TX.
  91           - description: Address and length of RX.
  92           - description: Address and length of PCS.
  93           - description: Address and length of TX2.
  94           - description: Address and length of RX2.
  95           - description: Address and length of pcs_misc.
  96
  97       clocks:
  98         items:
  99           - description: pipe clock
 100
 101       clock-names:
 102         items:
 103           - const: pipe0
 104
 105       clock-output-names:
 106         items:
 107           - const: usb3_phy_pipe_clk_src
 108
 109       '#clock-cells':
 110         const: 0
 111
 112       '#phy-cells':
 113         const: 0
 114
 115     required:
 116       - reg
 117       - clocks
 118       - clock-names
 119       - '#clock-cells'
 120       - '#phy-cells'
 121
 122   "^dp-phy@[0-9a-f]+$":
 123     type: object
 124     description:
 125       The DP PHY.
 126
 127     properties:
 128       reg:
 129         items:
 130           - description: Address and length of TX.
 131           - description: Address and length of RX.
 132           - description: Address and length of PCS.
 133           - description: Address and length of TX2.
 134           - description: Address and length of RX2.
 135
 136       '#clock-cells':
 137         const: 1
 138
 139       '#phy-cells':
 140         const: 0
 141
 142     required:
 143       - reg
 144       - '#clock-cells'
 145       - '#phy-cells'
 146
 147 required:
 148   - compatible
 149   - reg
 150   - "#clock-cells"
 151   - "#address-cells"
 152   - "#size-cells"
 153   - ranges
 154   - clocks
 155   - clock-names
 156   - resets
 157   - reset-names
 158   - vdda-phy-supply
 159   - vdda-pll-supply
 160
 161 additionalProperties: false
 162
 163 examples:
 164   - |
 165     #include <dt-bindings/clock/qcom,gcc-sdm845.h>
 166     usb_1_qmpphy: phy-wrapper@88e9000 {
 167         compatible = "qcom,sdm845-qmp-usb3-dp-phy";
 168         reg = <0x088e9000 0x18c>,
 169               <0x088e8000 0x10>,
 170               <0x088ea000 0x40>;
 171         reg-names = "usb", "dp_com", "dp";
 172         #clock-cells = <1>;
 173         #address-cells = <1>;
 174         #size-cells = <1>;
 175         ranges = <0x0 0x088e9000 0x2000>;
 176
 177         clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
 178                  <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
 179                  <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
 180                  <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
 181         clock-names = "aux", "cfg_ahb", "ref", "com_aux";
 182
 183         resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
 184                  <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
 185         reset-names = "phy", "common";
 186
 187         vdda-phy-supply = <&vdda_usb2_ss_1p2>;
 188         vdda-pll-supply = <&vdda_usb2_ss_core>;
 189
 190         usb3-phy@200 {
 191             reg = <0x200 0x128>,
 192                   <0x400 0x200>,
 193                   <0xc00 0x218>,
 194                   <0x600 0x128>,
 195                   <0x800 0x200>,
 196                   <0xa00 0x100>;
 197             #clock-cells = <0>;
 198             #phy-cells = <0>;
 199             clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
 200             clock-names = "pipe0";
 201             clock-output-names = "usb3_phy_pipe_clk_src";
 202         };
 203
 204         dp-phy@88ea200 {
 205             reg = <0xa200 0x200>,
 206                   <0xa400 0x200>,
 207                   <0xaa00 0x200>,
 208                   <0xa600 0x200>,
 209                   <0xa800 0x200>;
 210             #clock-cells = <1>;
 211             #phy-cells = <0>;
 212         };
 213     };