1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: STMicroelectronics STM32 USB HS PHY controller binding
11 The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
12 switch. It controls PHY configuration and status, and the UTMI+ switch that
13 selects either OTG or HOST controller for the second PHY port. It also sets
19 |_ PHY port#1 _________________ HOST controller
21 | / 1|________________|
22 |_ PHY port#2 ----| |________________
24 |_ UTMI switch_______| OTG controller
27 - Amelie Delaunay <amelie.delaunay@st.com>
31 const: st,stm32mp1-usbphyc
49 description: regulator providing 1V1 power supply to the PLL block
52 description: regulator providing 1V8 power supply to the PLL block
55 description: number of clock cells for ck_usbo_48m consumer
58 #Required child nodes:
64 Each port the controller provides must be represented as a sub-node.
68 description: phy port index.
72 description: regulator providing 3V3 power supply to the PHY.
80 - $ref: ../connector/usb-connector.yaml
98 The value is used to select UTMI switch output.
99 0 for OTG controller and 1 for Host controller.
106 additionalProperties: false
119 additionalProperties: false
123 #include <dt-bindings/clock/stm32mp1-clks.h>
124 #include <dt-bindings/reset/stm32mp1-resets.h>
125 usbphyc: usbphyc@5a006000 {
126 compatible = "st,stm32mp1-usbphyc";
127 reg = <0x5a006000 0x1000>;
128 clocks = <&rcc USBPHY_K>;
129 resets = <&rcc USBPHY_R>;
130 vdda1v1-supply = <®11>;
131 vdda1v8-supply = <®18>;
132 #address-cells = <1>;
136 usbphyc_port0: usb-phy@0 {
138 phy-supply = <&vdd_usb>;
141 compatible = "usb-a-connector";
142 vbus-supply = <&vbus_sw>;
146 usbphyc_port1: usb-phy@1 {
148 phy-supply = <&vdd_usb>;