Documentation/devicetree/bindings/phy/phy-stm32-usbphyc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/phy/phy-stm32-usbphyc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: STMicroelectronics STM32 USB HS PHY controller binding
   8
   9 description:
  10
  11   The STM32 USBPHYC block contains a dual port High Speed UTMI+ PHY and a UTMI
  12   switch. It controls PHY configuration and status, and the UTMI+ switch that
  13   selects either OTG or HOST controller for the second PHY port. It also sets
  14   PLL configuration.
  15
  16   USBPHYC
  17   |_ PLL
  18   |
  19   |_ PHY port#1 _________________ HOST controller
  20   |                   __                 |
  21   |                  / 1|________________|
  22   |_ PHY port#2 ----|   |________________
  23   |                  \_0|                |
  24   |_ UTMI switch_______|          OTG controller
  25
  26 maintainers:
  27   - Amelie Delaunay <amelie.delaunay@st.com>
  28
  29 properties:
  30   compatible:
  31     const: st,stm32mp1-usbphyc
  32
  33   reg:
  34     maxItems: 1
  35
  36   clocks:
  37     maxItems: 1
  38
  39   resets:
  40     maxItems: 1
  41
  42   "#address-cells":
  43     const: 1
  44
  45   "#size-cells":
  46     const: 0
  47
  48 #Required child nodes:
  49
  50 patternProperties:
  51   "^usb-phy@[0|1]$":
  52     type: object
  53     description:
  54       Each port the controller provides must be represented as a sub-node.
  55
  56     properties:
  57       reg:
  58         description: phy port index.
  59         maxItems: 1
  60
  61       phy-supply:
  62         description: regulator providing 3V3 power supply to the PHY.
  63
  64       vdda1v1-supply:
  65         description: regulator providing 1V1 power supply to the PLL block
  66
  67       vdda1v8-supply:
  68         description: regulator providing 1V8 power supply to the PLL block
  69
  70       "#phy-cells":
  71         enum: [ 0x0, 0x1 ]
  72
  73     allOf:
  74       - if:
  75           properties:
  76             reg:
  77               const: 0
  78         then:
  79           properties:
  80             "#phy-cells":
  81               const: 0
  82         else:
  83           properties:
  84             "#phy-cells":
  85               const: 1
  86               description:
  87                 The value is used to select UTMI switch output.
  88                 0 for OTG controller and 1 for Host controller.
  89
  90     required:
  91       - reg
  92       - phy-supply
  93       - vdda1v1-supply
  94       - vdda1v8-supply
  95       - "#phy-cells"
  96
  97     additionalProperties: false
  98
  99 required:
 100   - compatible
 101   - reg
 102   - clocks
 103   - "#address-cells"
 104   - "#size-cells"
 105   - usb-phy@0
 106   - usb-phy@1
 107
 108 additionalProperties: false
 109
 110 examples:
 111   - |
 112     #include <dt-bindings/clock/stm32mp1-clks.h>
 113     #include <dt-bindings/reset/stm32mp1-resets.h>
 114     usbphyc: usbphyc@5a006000 {
 115         compatible = "st,stm32mp1-usbphyc";
 116         reg = <0x5a006000 0x1000>;
 117         clocks = <&rcc USBPHY_K>;
 118         resets = <&rcc USBPHY_R>;
 119         #address-cells = <1>;
 120         #size-cells = <0>;
 121
 122         usbphyc_port0: usb-phy@0 {
 123             reg = <0>;
 124             phy-supply = <&vdd_usb>;
 125             vdda1v1-supply = <&reg11>;
 126             vdda1v8-supply = <&reg18>;
 127             #phy-cells = <0>;
 128         };
 129
 130         usbphyc_port1: usb-phy@1 {
 131             reg = <1>;
 132             phy-supply = <&vdd_usb>;
 133             vdda1v1-supply = <&reg11>;
 134             vdda1v8-supply = <&reg18>;
 135             #phy-cells = <1>;
 136         };
 137     };
 138 ...