Smack: Handle io_uring kernel thread privileges
[linux-2.6-microblaze.git] / Documentation / devicetree / bindings / phy / brcm-sata-phy.txt
1 * Broadcom SATA3 PHY
2
3 Required properties:
4 - compatible: should be one or more of
5      "brcm,bcm7216-sata-phy"
6      "brcm,bcm7425-sata-phy"
7      "brcm,bcm7445-sata-phy"
8      "brcm,iproc-ns2-sata-phy"
9      "brcm,iproc-nsp-sata-phy"
10      "brcm,phy-sata3"
11      "brcm,iproc-sr-sata-phy"
12      "brcm,bcm63138-sata-phy"
13 - address-cells: should be 1
14 - size-cells: should be 0
15 - reg: register ranges for the PHY PCB interface
16 - reg-names: should be "phy" and "phy-ctrl"
17      The "phy-ctrl" registers are only required for
18      "brcm,iproc-ns2-sata-phy" and "brcm,iproc-sr-sata-phy".
19
20 Sub-nodes:
21   Each port's PHY should be represented as a sub-node.
22
23 Sub-nodes required properties:
24 - reg: the PHY number
25 - phy-cells: generic PHY binding; must be 0
26
27 Sub-nodes optional properties:
28 - brcm,enable-ssc: use spread spectrum clocking (SSC) on this port
29      This property is not applicable for "brcm,iproc-ns2-sata-phy",
30      "brcm,iproc-nsp-sata-phy" and "brcm,iproc-sr-sata-phy".
31
32 - brcm,rxaeq-mode: string that indicates the desired RX equalizer
33   mode, possible values are:
34         "off" (equivalent to not specifying the property)
35         "auto"
36         "manual" (brcm,rxaeq-value is used in that case)
37
38 - brcm,rxaeq-value: when 'rxaeq-mode' is set to "manual", provides the RX
39   equalizer value that should be used. Allowed range is 0..63.
40
41 Example
42         sata-phy@f0458100 {
43                 compatible = "brcm,bcm7445-sata-phy", "brcm,phy-sata3";
44                 reg = <0xf0458100 0x1e00>, <0xf045804c 0x10>;
45                 reg-names = "phy";
46                 #address-cells = <1>;
47                 #size-cells = <0>;
48
49                 sata-phy@0 {
50                         reg = <0>;
51                         #phy-cells = <0>;
52                 };
53
54                 sata-phy@1 {
55                         reg = <1>;
56                         #phy-cells = <0>;
57                 };
58         };