Documentation/devicetree/bindings/perf/arm,cmn.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright 2020 Arm Ltd.
   3 %YAML 1.2
   4 ---
   5 $id: http://devicetree.org/schemas/perf/arm,cmn.yaml#
   6 $schema: http://devicetree.org/meta-schemas/core.yaml#
   7
   8 title: Arm CMN (Coherent Mesh Network) Performance Monitors
   9
  10 maintainers:
  11   - Robin Murphy <robin.murphy@arm.com>
  12
  13 properties:
  14   compatible:
  15     const: arm,cmn-600
  16
  17   reg:
  18     items:
  19       - description: Physical address of the base (PERIPHBASE) and
  20           size (up to 64MB) of the configuration address space.
  21
  22   interrupts:
  23     minItems: 1
  24     items:
  25       - description: Overflow interrupt for DTC0
  26       - description: Overflow interrupt for DTC1
  27       - description: Overflow interrupt for DTC2
  28       - description: Overflow interrupt for DTC3
  29     description: One interrupt for each DTC domain implemented must
  30       be specified, in order. DTC0 is always present.
  31
  32   arm,root-node:
  33     $ref: /schemas/types.yaml#/definitions/uint32
  34     description: Offset from PERIPHBASE of the configuration
  35       discovery node (see TRM definition of ROOTNODEBASE).
  36
  37 required:
  38   - compatible
  39   - reg
  40   - interrupts
  41   - arm,root-node
  42
  43 additionalProperties: false
  44
  45 examples:
  46   - |
  47     #include <dt-bindings/interrupt-controller/arm-gic.h>
  48     #include <dt-bindings/interrupt-controller/irq.h>
  49     pmu@50000000 {
  50         compatible = "arm,cmn-600";
  51         reg = <0x50000000 0x4000000>;
  52         /* 4x2 mesh with one DTC, and CFG node at 0,1,1,0 */
  53         interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
  54         arm,root-node = <0x104000>;
  55     };
  56 ...