Documentation/devicetree/bindings/pci/socionext,uniphier-pcie-ep.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/socionext,uniphier-pcie-ep.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Socionext UniPhier PCIe endpoint controller
   8
   9 description: |
  10   UniPhier PCIe endpoint controller is based on the Synopsys DesignWare
  11   PCI core. It shares common features with the PCIe DesignWare core and
  12   inherits common properties defined in
  13   Documentation/devicetree/bindings/pci/snps,dw-pcie-ep.yaml.
  14
  15 maintainers:
  16   - Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
  17
  18 allOf:
  19   - $ref: /schemas/pci/snps,dw-pcie-ep.yaml#
  20
  21 properties:
  22   compatible:
  23     const: socionext,uniphier-pro5-pcie-ep
  24
  25   reg:
  26     minItems: 4
  27     maxItems: 5
  28
  29   reg-names:
  30     oneOf:
  31       - items:
  32           - const: dbi
  33           - const: dbi2
  34           - const: link
  35           - const: addr_space
  36       - items:
  37           - const: dbi
  38           - const: dbi2
  39           - const: link
  40           - const: addr_space
  41           - const: atu
  42
  43   clocks:
  44     maxItems: 2
  45
  46   clock-names:
  47     items:
  48       - const: gio
  49       - const: link
  50
  51   resets:
  52     maxItems: 2
  53
  54   reset-names:
  55     items:
  56       - const: gio
  57       - const: link
  58
  59   num-ib-windows:
  60     const: 16
  61
  62   num-ob-windows:
  63     const: 16
  64
  65   num-lanes: true
  66
  67   phys:
  68     maxItems: 1
  69
  70   phy-names:
  71     const: pcie-phy
  72
  73 required:
  74   - compatible
  75   - reg
  76   - reg-names
  77   - clocks
  78   - clock-names
  79   - resets
  80   - reset-names
  81
  82 additionalProperties: false
  83
  84 examples:
  85   - |
  86     pcie_ep: pcie-ep@66000000 {
  87         compatible = "socionext,uniphier-pro5-pcie-ep";
  88         reg-names = "dbi", "dbi2", "link", "addr_space";
  89         reg = <0x66000000 0x1000>, <0x66001000 0x1000>,
  90               <0x66010000 0x10000>, <0x67000000 0x400000>;
  91         clock-names = "gio", "link";
  92         clocks = <&sys_clk 12>, <&sys_clk 24>;
  93         reset-names = "gio", "link";
  94         resets = <&sys_rst 12>, <&sys_rst 24>;
  95         num-ib-windows = <16>;
  96         num-ob-windows = <16>;
  97         num-lanes = <4>;
  98         phy-names = "pcie-phy";
  99         phys = <&pcie_phy>;
 100     };