Documentation/devicetree/bindings/pci/sifive,fu740-pcie.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/sifive,fu740-pcie.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: SiFive FU740 PCIe host controller
   8
   9 description: |+
  10   SiFive FU740 PCIe host controller is based on the Synopsys DesignWare
  11   PCI core. It shares common features with the PCIe DesignWare core and
  12   inherits common properties defined in
  13   Documentation/devicetree/bindings/pci/snps,dw-pcie.yaml.
  14
  15 maintainers:
  16   - Paul Walmsley <paul.walmsley@sifive.com>
  17   - Greentime Hu <greentime.hu@sifive.com>
  18
  19 allOf:
  20   - $ref: /schemas/pci/snps,dw-pcie.yaml#
  21
  22 properties:
  23   compatible:
  24     const: sifive,fu740-pcie
  25
  26   reg:
  27     maxItems: 3
  28
  29   reg-names:
  30     items:
  31       - const: dbi
  32       - const: config
  33       - const: mgmt
  34
  35   num-lanes:
  36     const: 8
  37
  38   msi-parent: true
  39
  40   interrupt-names:
  41     items:
  42       - const: msi
  43       - const: inta
  44       - const: intb
  45       - const: intc
  46       - const: intd
  47
  48   resets:
  49     description: A phandle to the PCIe power up reset line.
  50     maxItems: 1
  51
  52   pwren-gpios:
  53     description: Should specify the GPIO for controlling the PCI bus device power on.
  54     maxItems: 1
  55
  56   reset-gpios:
  57     maxItems: 1
  58
  59 required:
  60   - dma-coherent
  61   - num-lanes
  62   - interrupts
  63   - interrupt-names
  64   - interrupt-parent
  65   - interrupt-map-mask
  66   - interrupt-map
  67   - clock-names
  68   - clocks
  69   - resets
  70   - pwren-gpios
  71   - reset-gpios
  72
  73 unevaluatedProperties: false
  74
  75 examples:
  76   - |
  77     bus {
  78         #address-cells = <2>;
  79         #size-cells = <2>;
  80         #include <dt-bindings/clock/sifive-fu740-prci.h>
  81
  82         pcie@e00000000 {
  83             compatible = "sifive,fu740-pcie";
  84             #address-cells = <3>;
  85             #size-cells = <2>;
  86             #interrupt-cells = <1>;
  87             reg = <0xe 0x00000000 0x0 0x80000000>,
  88                   <0xd 0xf0000000 0x0 0x10000000>,
  89                   <0x0 0x100d0000 0x0 0x1000>;
  90             reg-names = "dbi", "config", "mgmt";
  91             device_type = "pci";
  92             dma-coherent;
  93             bus-range = <0x0 0xff>;
  94             ranges = <0x81000000  0x0 0x60080000  0x0 0x60080000 0x0 0x10000>,      /* I/O */
  95                      <0x82000000  0x0 0x60090000  0x0 0x60090000 0x0 0xff70000>,    /* mem */
  96                      <0x82000000  0x0 0x70000000  0x0 0x70000000 0x0 0x1000000>,    /* mem */
  97                      <0xc3000000 0x20 0x00000000 0x20 0x00000000 0x20 0x00000000>;  /* mem prefetchable */
  98             num-lanes = <0x8>;
  99             interrupts = <56>, <57>, <58>, <59>, <60>, <61>, <62>, <63>, <64>;
 100             interrupt-names = "msi", "inta", "intb", "intc", "intd";
 101             interrupt-parent = <&plic0>;
 102             interrupt-map-mask = <0x0 0x0 0x0 0x7>;
 103             interrupt-map = <0x0 0x0 0x0 0x1 &plic0 57>,
 104                             <0x0 0x0 0x0 0x2 &plic0 58>,
 105                             <0x0 0x0 0x0 0x3 &plic0 59>,
 106                             <0x0 0x0 0x0 0x4 &plic0 60>;
 107             clock-names = "pcie_aux";
 108             clocks = <&prci PRCI_CLK_PCIE_AUX>;
 109             resets = <&prci 4>;
 110             pwren-gpios = <&gpio 5 0>;
 111             reset-gpios = <&gpio 8 0>;
 112         };
 113     };