Documentation/devicetree/bindings/pci/microchip,pcie-host.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/pci/microchip,pcie-host.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Microchip PCIe Root Port Bridge Controller Device Tree Bindings
   8
   9 maintainers:
  10   - Daire McNamara <daire.mcnamara@microchip.com>
  11
  12 allOf:
  13   - $ref: /schemas/pci/pci-bus.yaml#
  14
  15 properties:
  16   compatible:
  17     const: microchip,pcie-host-1.0 # PolarFire
  18
  19   reg:
  20     maxItems: 2
  21
  22   reg-names:
  23     items:
  24       - const: cfg
  25       - const: apb
  26
  27   interrupts:
  28     minItems: 1
  29     items:
  30       - description: PCIe host controller
  31       - description: builtin MSI controller
  32
  33   interrupt-names:
  34     minItems: 1
  35     items:
  36       - const: pcie
  37       - const: msi
  38
  39   ranges:
  40     maxItems: 1
  41
  42   msi-controller:
  43     description: Identifies the node as an MSI controller.
  44
  45   msi-parent:
  46     description: MSI controller the device is capable of using.
  47
  48 required:
  49   - reg
  50   - reg-names
  51   - "#interrupt-cells"
  52   - interrupts
  53   - interrupt-map-mask
  54   - interrupt-map
  55   - msi-controller
  56
  57 unevaluatedProperties: false
  58
  59 examples:
  60   - |
  61     soc {
  62             #address-cells = <2>;
  63             #size-cells = <2>;
  64             pcie0: pcie@2030000000 {
  65                     compatible = "microchip,pcie-host-1.0";
  66                     reg = <0x0 0x70000000 0x0 0x08000000>,
  67                           <0x0 0x43000000 0x0 0x00010000>;
  68                     reg-names = "cfg", "apb";
  69                     device_type = "pci";
  70                     #address-cells = <3>;
  71                     #size-cells = <2>;
  72                     #interrupt-cells = <1>;
  73                     interrupts = <119>;
  74                     interrupt-map-mask = <0x0 0x0 0x0 0x7>;
  75                     interrupt-map = <0 0 0 1 &pcie_intc0 0>,
  76                                     <0 0 0 2 &pcie_intc0 1>,
  77                                     <0 0 0 3 &pcie_intc0 2>,
  78                                     <0 0 0 4 &pcie_intc0 3>;
  79                     interrupt-parent = <&plic0>;
  80                     msi-parent = <&pcie0>;
  81                     msi-controller;
  82                     bus-range = <0x00 0x7f>;
  83                     ranges = <0x03000000 0x0 0x78000000 0x0 0x78000000 0x0 0x04000000>;
  84                     pcie_intc0: interrupt-controller {
  85                         #address-cells = <0>;
  86                         #interrupt-cells = <1>;
  87                         interrupt-controller;
  88                     };
  89             };
  90     };