Documentation/devicetree/bindings/pci/kirin-pcie.txt

   1 HiSilicon Kirin SoCs PCIe host DT description
   2
   3 Kirin PCIe host controller is based on the Synopsys DesignWare PCI core.
   4 It shares common functions with the PCIe DesignWare core driver and
   5 inherits common properties defined in
   6 Documentation/devicetree/bindings/pci/designware-pcie.txt.
   7
   8 Additional properties are described here:
   9
  10 Required properties
  11 - compatible:
  12         "hisilicon,kirin960-pcie" for PCIe of Kirin960 SoC
  13 - reg: Should contain rc_dbi, apb, phy, config registers location and length.
  14 - reg-names: Must include the following entries:
  15   "dbi": controller configuration registers;
  16   "apb": apb Ctrl register defined by Kirin;
  17   "phy": apb PHY register defined by Kirin;
  18   "config": PCIe configuration space registers.
  19 - reset-gpios: The GPIO to generate PCIe PERST# assert and deassert signal.
  20
  21 Optional properties:
  22
  23 Example based on kirin960:
  24
  25         pcie@f4000000 {
  26                 compatible = "hisilicon,kirin-pcie";
  27                 reg = <0x0 0xf4000000 0x0 0x1000>, <0x0 0xff3fe000 0x0 0x1000>,
  28                       <0x0 0xf3f20000 0x0 0x40000>, <0x0 0xF4000000 0 0x2000>;
  29                 reg-names = "dbi","apb","phy", "config";
  30                 bus-range = <0x0  0x1>;
  31                 #address-cells = <3>;
  32                 #size-cells = <2>;
  33                 device_type = "pci";
  34                 ranges = <0x02000000 0x0 0x00000000 0x0 0xf5000000 0x0 0x2000000>;
  35                 num-lanes = <1>;
  36                 #interrupt-cells = <1>;
  37                 interrupt-map-mask = <0xf800 0 0 7>;
  38                 interrupt-map = <0x0 0 0 1 &gic 0 0 0  282 4>,
  39                                 <0x0 0 0 2 &gic 0 0 0  283 4>,
  40                                 <0x0 0 0 3 &gic 0 0 0  284 4>,
  41                                 <0x0 0 0 4 &gic 0 0 0  285 4>;
  42                 clocks = <&crg_ctrl HI3660_PCIEPHY_REF>,
  43                          <&crg_ctrl HI3660_CLK_GATE_PCIEAUX>,
  44                          <&crg_ctrl HI3660_PCLK_GATE_PCIE_PHY>,
  45                          <&crg_ctrl HI3660_PCLK_GATE_PCIE_SYS>,
  46                          <&crg_ctrl HI3660_ACLK_GATE_PCIE>;
  47                 clock-names = "pcie_phy_ref", "pcie_aux",
  48                               "pcie_apb_phy", "pcie_apb_sys", "pcie_aclk";
  49                 reset-gpios = <&gpio11 1 0 >;
  50         };