1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/opp/allwinner,sun50i-h6-operating-points.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Allwinner H6 CPU OPP Device Tree Bindings
10 - Chen-Yu Tsai <wens@csie.org>
11 - Maxime Ripard <mripard@kernel.org>
14 For some SoCs, the CPU frequency subset and voltage value of each
15 OPP varies based on the silicon variant in use. Allwinner Process
16 Voltage Scaling Tables defines the voltage and frequency value based
17 on the speedbin blown in the efuse combination. The
18 sun50i-cpufreq-nvmem driver reads the efuse value from the SoC to
19 provide the OPP framework with required information.
22 - $ref: opp-v2-base.yaml#
26 const: allwinner,sun50i-h6-operating-points
30 A phandle pointing to a nvmem-cells node representing the efuse
31 registers that has information about the speedbin that is used
32 to select the right frequency/voltage value pair. Please refer
33 the for nvmem-cells bindings
34 Documentation/devicetree/bindings/nvmem/nvmem.txt and also
49 clock-latency-ns: true
52 "opp-microvolt-.*": true
56 - opp-microvolt-speed0
57 - opp-microvolt-speed1
58 - opp-microvolt-speed2
60 unevaluatedProperties: false
62 additionalProperties: false
66 cpu_opp_table: opp-table {
67 compatible = "allwinner,sun50i-h6-operating-points";
68 nvmem-cells = <&speedbin_efuse>;
72 clock-latency-ns = <244144>; /* 8 32k periods */
73 opp-hz = /bits/ 64 <480000000>;
75 opp-microvolt-speed0 = <880000>;
76 opp-microvolt-speed1 = <820000>;
77 opp-microvolt-speed2 = <800000>;
81 clock-latency-ns = <244144>; /* 8 32k periods */
82 opp-hz = /bits/ 64 <720000000>;
84 opp-microvolt-speed0 = <880000>;
85 opp-microvolt-speed1 = <820000>;
86 opp-microvolt-speed2 = <800000>;
90 clock-latency-ns = <244144>; /* 8 32k periods */
91 opp-hz = /bits/ 64 <816000000>;
93 opp-microvolt-speed0 = <880000>;
94 opp-microvolt-speed1 = <820000>;
95 opp-microvolt-speed2 = <800000>;
99 clock-latency-ns = <244144>; /* 8 32k periods */
100 opp-hz = /bits/ 64 <888000000>;
102 opp-microvolt-speed0 = <940000>;
103 opp-microvolt-speed1 = <820000>;
104 opp-microvolt-speed2 = <800000>;
108 clock-latency-ns = <244144>; /* 8 32k periods */
109 opp-hz = /bits/ 64 <1080000000>;
111 opp-microvolt-speed0 = <1060000>;
112 opp-microvolt-speed1 = <880000>;
113 opp-microvolt-speed2 = <840000>;
117 clock-latency-ns = <244144>; /* 8 32k periods */
118 opp-hz = /bits/ 64 <1320000000>;
120 opp-microvolt-speed0 = <1160000>;
121 opp-microvolt-speed1 = <940000>;
122 opp-microvolt-speed2 = <900000>;
126 clock-latency-ns = <244144>; /* 8 32k periods */
127 opp-hz = /bits/ 64 <1488000000>;
129 opp-microvolt-speed0 = <1160000>;
130 opp-microvolt-speed1 = <1000000>;
131 opp-microvolt-speed2 = <960000>;