1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: http://devicetree.org/schemas/net/can/renesas,rcar-canfd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: Renesas R-Car CAN FD Controller
10 - Fabrizio Castro <fabrizio.castro.jz@renesas.com>
13 - $ref: can-controller.yaml#
20 - renesas,r8a774a1-canfd # RZ/G2M
21 - renesas,r8a774b1-canfd # RZ/G2N
22 - renesas,r8a774c0-canfd # RZ/G2E
23 - renesas,r8a774e1-canfd # RZ/G2H
24 - renesas,r8a7795-canfd # R-Car H3
25 - renesas,r8a7796-canfd # R-Car M3-W
26 - renesas,r8a77965-canfd # R-Car M3-N
27 - renesas,r8a77970-canfd # R-Car V3M
28 - renesas,r8a77980-canfd # R-Car V3H
29 - renesas,r8a77990-canfd # R-Car E3
30 - renesas,r8a77995-canfd # R-Car D3
31 - const: renesas,rcar-gen3-canfd # R-Car Gen3 and RZ/G2
35 - renesas,r9a07g044-canfd # RZ/G2{L,LC}
36 - const: renesas,rzg2l-canfd # RZ/G2L family
58 $ref: /schemas/types.yaml#/definitions/flag
60 The controller can operate in either CAN FD only mode (default) or
61 Classical CAN only mode. The mode is global to both the channels.
62 Specify this property to put the controller in Classical CAN only mode.
66 Reference to the CANFD clock. The CANFD clock is a div6 clock and can be
67 used by both CAN (if present) and CAN FD controllers at the same time.
68 It needs to be scaled to maximum frequency if any of these controllers
72 description: Maximum frequency of the CANFD clock.
78 The controller supports two channels and each is represented as a child
79 node. Each child node supports the "status" property only, which
80 is used to enable/disable the respective channel.
91 - assigned-clock-rates
100 - renesas,rzg2l-canfd
105 - description: CAN global error interrupt
106 - description: CAN receive FIFO interrupt
107 - description: CAN0 error interrupt
108 - description: CAN0 transmit interrupt
109 - description: CAN0 transmit/receive FIFO receive completion interrupt
110 - description: CAN1 error interrupt
111 - description: CAN1 transmit interrupt
112 - description: CAN1 transmit/receive FIFO receive completion interrupt
140 - description: Channel interrupt
141 - description: Global interrupt
151 unevaluatedProperties: false
155 #include <dt-bindings/clock/r8a7795-cpg-mssr.h>
156 #include <dt-bindings/interrupt-controller/arm-gic.h>
157 #include <dt-bindings/power/r8a7795-sysc.h>
159 canfd: can@e66c0000 {
160 compatible = "renesas,r8a7795-canfd",
161 "renesas,rcar-gen3-canfd";
162 reg = <0xe66c0000 0x8000>;
163 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>,
164 <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&cpg CPG_MOD 914>,
166 <&cpg CPG_CORE R8A7795_CLK_CANFD>,
168 clock-names = "fck", "canfd", "can_clk";
169 assigned-clocks = <&cpg CPG_CORE R8A7795_CLK_CANFD>;
170 assigned-clock-rates = <40000000>;
171 power-domains = <&sysc R8A7795_PD_ALWAYS_ON>;