1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: NAND Chip and NAND Controller Generic Binding
10 - Miquel Raynal <miquel.raynal@bootlin.com>
11 - Richard Weinberger <richard@nod.at>
14 The NAND controller should be represented with its own DT node, and
15 all NAND chips attached to this controller should be defined as
16 children nodes of the NAND controller. This representation should be
17 enforced even for simple controllers supporting only one chip.
19 The ECC strength and ECC step size properties define the user
20 desires in terms of correction capability of a controller. Together,
21 they request the ECC engine to correct {strength} bit errors per
24 The interpretation of these parameters is implementation-defined, so
25 not all implementations must support all possible
26 combinations. However, implementations are encouraged to further
27 specify the value(s) they support.
31 pattern: "^nand-controller(@.*)?"
45 Array of chip-select available to the controller. The first
46 entries are a 1:1 mapping of the available chip-select on the
47 NAND controller (even if they are not used). As many additional
48 chip-select as needed may follow and should be phandles of GPIO
49 lines. 'reg' entries of the NAND chip subnodes become indexes of
50 this array when this property is present.
58 Contains the native Ready/Busy IDs.
62 - $ref: /schemas/types.yaml#/definitions/phandle
64 A phandle on the hardware ECC engine if any. There are
65 basically three possibilities:
66 1/ The ECC engine is part of the NAND controller, in this
67 case the phandle should reference the parent node.
68 2/ The ECC engine is part of the NAND part (on-die), in this
69 case the phandle should reference the node itself.
70 3/ The ECC engine is external, in this case the phandle should
71 reference the specific ECC engine node.
73 nand-use-soft-ecc-engine:
75 description: Use a software ECC engine.
79 description: Do not use any ECC correction.
83 - $ref: /schemas/types.yaml#/definitions/string
84 - enum: [ oob, interleaved ]
86 Location of the ECC bytes. This location is unknown by default
87 but can be explicitly set to "oob", if all ECC bytes are
88 known to be stored in the OOB area, or "interleaved" if ECC
89 bytes will be interleaved with regular data in the main area.
93 Desired ECC algorithm.
94 $ref: /schemas/types.yaml#/definitions/string
95 enum: [hamming, bch, rs]
99 Bus width to the NAND chip
100 $ref: /schemas/types.yaml#/definitions/uint32
105 $ref: /schemas/types.yaml#/definitions/flag
107 With this property, the OS will search the device for a Bad
108 Block Table (BBT). If not found, it will create one, reserve
109 a few blocks at the end of the device to store it and update
110 it as the device ages. Otherwise, the out-of-band area of a
111 few pages of all the blocks will be scanned at boot time to
112 find Bad Block Markers (BBM). These markers will help to
113 build a volatile BBT in RAM.
117 Maximum number of bits that can be corrected per ECC step.
118 $ref: /schemas/types.yaml#/definitions/uint32
123 Number of data bytes covered by a single ECC step.
124 $ref: /schemas/types.yaml#/definitions/uint32
128 $ref: /schemas/types.yaml#/definitions/flag
130 Whether or not the ECC strength should be maximized. The
131 maximum ECC strength is both controller and chip
132 dependent. The ECC engine has to select the ECC config
133 providing the best strength and taking the OOB area size
134 constraint into account. This is particularly useful when
135 only the in-band area is used by the upper layers, and you
136 want to make your NAND as reliable as possible.
139 $ref: /schemas/types.yaml#/definitions/flag
141 Whether or not the NAND chip is a boot medium. Drivers might
142 use this information to select ECC algorithms supported by
143 the boot ROM or similar restrictions.
146 $ref: /schemas/types.yaml#/definitions/uint32-array
148 Contains the native Ready/Busy IDs.
152 Contains one or more GPIO descriptor (the numper of descriptor
153 depends on the number of R/B pins exposed by the flash) for the
154 Ready/Busy pins. Active state refers to the NAND ready state and
155 should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
158 $ref: /schemas/types.yaml#/definitions/uint64-matrix
160 Regions in the NAND chip which are protected using a secure element
161 like Trustzone. This property contains the start address and size of
162 the secure regions present.
171 additionalProperties: true
176 #address-cells = <1>;
178 cs-gpios = <0>, <&gpioA 1>; /* A single native CS is available */
180 /* controller specific properties */
183 reg = <0>; /* Native CS */
184 nand-use-soft-ecc-engine;
185 nand-ecc-algo = "bch";
187 /* controller specific properties */
191 reg = <1>; /* GPIO CS */