1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mtd/mtd-physmap.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: CFI or JEDEC memory-mapped NOR flash, MTD-RAM (NVRAM...)
10 - Rob Herring <robh@kernel.org>
13 Flash chips (Memory Technology Devices) are often used for solid state
14 file systems on embedded devices.
27 - cortina,gemini-flash
29 - ge,imp3a-firmware-mirror
30 - ge,imp3a-paged-flash
31 - gef,ppc9a-firmware-mirror
32 - gef,ppc9a-paged-flash
33 - gef,sbc310-firmware-mirror
34 - gef,sbc310-paged-flash
35 - gef,sbc610-firmware-mirror
36 - gef,sbc610-paged-flash
42 - intel,PC28F640P30T85
46 - xlnx,xps-mch-emc-2.00.a
50 - cypress,cy7c1019dv33-10zsxi
61 It's possible to (optionally) define multiple "reg" tuples so that
62 non-identical chips can be described in one node.
67 description: Width (in bytes) of the bank. Equal to the device width times
68 the number of interleaved chips.
69 $ref: /schemas/types.yaml#/definitions/uint32
74 Width of a single mtd chip. If omitted, assumed to be equal to 'bank-width'.
75 $ref: /schemas/types.yaml#/definitions/uint32
78 no-unaligned-direct-access:
81 Disables the default direct mapping of the flash.
83 On some platforms (e.g. MPC5200) a direct 1:1 mapping may cause problems
84 with JFFS2 usage, as the local bus (LPB) doesn't support unaligned
85 accesses as implemented in the JFFS2 code via memcpy(). By defining
86 "no-unaligned-direct-access", the flash will not be exposed directly to
87 the MTD users (e.g. JFFS2) any more.
91 Allows specifying the mtd name for retro capability with physmap-flash
92 drivers as boot loader pass the mtd partition via the old device name
94 $ref: /schemas/types.yaml#/definitions/string
96 use-advanced-sector-protection:
99 Enables support for the advanced sector protection (Spansion: PPB -
100 Persistent Protection Bits) locking.
103 description: The chip's physical erase block size in bytes.
104 $ref: /schemas/types.yaml#/definitions/uint32
108 List of GPIO descriptors that will be used to address the MSBs address
109 lines. The order goes from LSB to MSB.
124 $ref: partitions/partition.yaml
130 # FIXME: A parent bus may define timing properties
131 additionalProperties: true
137 compatible = "cfi-flash";
138 reg = <0xff000000 0x01000000>;
142 #address-cells = <1>;
144 ranges = <0 0xff000000 0x01000000>;
152 reg = <0xf80000 0x80000>;
158 /* An example with multiple "reg" tuples */
161 compatible = "intel,PC28F640P30T85", "cfi-flash";
162 reg = <0x00000000 0x02000000>,
163 <0x02000000 0x02000000>;
166 #address-cells = <1>;
168 ranges = <0 0 0x04000000>;
171 label = "test-part1";
172 reg = <0 0x04000000>;
177 /* An example using SRAM */
179 #address-cells = <2>;
183 compatible = "mtd-ram";
184 reg = <2 0 0x00200000>;
190 /* An example using addr-gpios */
191 #include <dt-bindings/gpio/gpio.h>
194 compatible = "cfi-flash";
195 reg = <0x20000000 0x02000000>;
197 addr-gpios = <&gpio1 2 GPIO_ACTIVE_HIGH>;
199 #address-cells = <1>;
201 ranges = <0 0x00000000 0x02000000>,
202 <1 0x02000000 0x02000000>;
205 label = "test-part1";
206 reg = <0 0x04000000>;