1 # SPDX-License-Identifier: GPL-2.0-only
4 $id: http://devicetree.org/schemas/mtd/jedec,spi-nor.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: SPI NOR flash ST M25Pxx (and similar) serial flash chips
10 - Rob Herring <robh@kernel.org>
19 - pattern: "^((((micron|spansion|st),)?\
20 (m25p(40|80|16|32|64|128)|\
21 n25q(32b|064|128a11|128a13|256a|512a|164k)))|\
22 atmel,at25df(321a|641|081a)|\
23 everspin,mr25h(10|40|128|256)|\
24 (mxicy|macronix),mx25l(4005a|1606e|6405d|8005|12805d|25635e)|\
25 (mxicy|macronix),mx25u(4033|4035)|\
26 (spansion,)?s25fl(128s|256s1|512s|008k|064k|164k)|\
27 (sst|microchip),sst25vf(016b|032b|040b)|\
29 (sst,)?sst25wf(040b|080)|\
31 (winbond,)?w25q(16|32(w|dw)?|64(dw)?|80bl|128(fw)?|256))$"
32 - const: jedec,spi-nor
42 - const: jedec,spi-nor
43 - const: jedec,spi-nor
45 Must also include "jedec,spi-nor" for any SPI NOR flash that can be
46 identified by the JEDEC READ ID opcode (0x9F).
51 spi-max-frequency: true
52 spi-rx-bus-width: true
53 spi-tx-bus-width: true
58 Use the "fast read" opcode to read data from the chip instead of the usual
59 "read" opcode. This opcode is not supported by all chips and support for
60 it can not be detected at runtime. Refer to your chips' datasheet to check
61 if this is supported by your chip.
66 Some flash devices utilize stateful addressing modes (e.g., for 32-bit
67 addressing) which need to be managed carefully by a system. Because these
68 sorts of flash don't have a standardized software reset command, and
69 because some systems don't toggle the flash RESET# pin upon system reset
70 (if the pin even exists at all), there are systems which cannot reboot
71 properly if the flash is left in the "wrong" state. This boolean flag can
72 be used on such systems, to denote the absence of a reliable reset
80 '#address-cells': true
84 # Note: use 'partitions' node for new users
91 additionalProperties: false
100 #address-cells = <1>;
102 compatible = "spansion,m25p80", "jedec,spi-nor";
104 spi-max-frequency = <40000000>;