Documentation/devicetree/bindings/mmc/sdhci-am654.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
   3 %YAML 1.2
   4 ---
   5 $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
   6 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   7
   8 title: TI AM654 MMC Controller
   9
  10 maintainers:
  11   - Ulf Hansson <ulf.hansson@linaro.org>
  12
  13 allOf:
  14   - $ref: mmc-controller.yaml#
  15
  16 properties:
  17   compatible:
  18     oneOf:
  19       - const: ti,am654-sdhci-5.1
  20       - const: ti,j721e-sdhci-8bit
  21       - const: ti,j721e-sdhci-4bit
  22       - const: ti,am64-sdhci-8bit
  23       - const: ti,am64-sdhci-4bit
  24       - items:
  25           - const: ti,j7200-sdhci-8bit
  26           - const: ti,j721e-sdhci-8bit
  27       - items:
  28           - const: ti,j7200-sdhci-4bit
  29           - const: ti,j721e-sdhci-4bit
  30
  31   reg:
  32     maxItems: 2
  33
  34   interrupts:
  35     maxItems: 1
  36
  37   power-domains:
  38     maxItems: 1
  39
  40   clocks:
  41     minItems: 1
  42     maxItems: 2
  43     description: Handles to input clocks
  44
  45   clock-names:
  46     minItems: 1
  47     items:
  48       - const: clk_ahb
  49       - const: clk_xin
  50
  51   # PHY output tap delays:
  52   # Used to delay the data valid window and align it to the sampling clock.
  53   # Binding needs to be provided for each supported speed mode otherwise the
  54   # corresponding mode will be disabled.
  55
  56   ti,otap-del-sel-legacy:
  57     description: Output tap delay for SD/MMC legacy timing
  58     $ref: "/schemas/types.yaml#/definitions/uint32"
  59     minimum: 0
  60     maximum: 0xf
  61
  62   ti,otap-del-sel-mmc-hs:
  63     description: Output tap delay for MMC high speed timing
  64     $ref: "/schemas/types.yaml#/definitions/uint32"
  65     minimum: 0
  66     maximum: 0xf
  67
  68   ti,otap-del-sel-sd-hs:
  69     description: Output tap delay for SD high speed timing
  70     $ref: "/schemas/types.yaml#/definitions/uint32"
  71     minimum: 0
  72     maximum: 0xf
  73
  74   ti,otap-del-sel-sdr12:
  75     description: Output tap delay for SD UHS SDR12 timing
  76     $ref: "/schemas/types.yaml#/definitions/uint32"
  77     minimum: 0
  78     maximum: 0xf
  79
  80   ti,otap-del-sel-sdr25:
  81     description: Output tap delay for SD UHS SDR25 timing
  82     $ref: "/schemas/types.yaml#/definitions/uint32"
  83     minimum: 0
  84     maximum: 0xf
  85
  86   ti,otap-del-sel-sdr50:
  87     description: Output tap delay for SD UHS SDR50 timing
  88     $ref: "/schemas/types.yaml#/definitions/uint32"
  89     minimum: 0
  90     maximum: 0xf
  91
  92   ti,otap-del-sel-sdr104:
  93     description: Output tap delay for SD UHS SDR104 timing
  94     $ref: "/schemas/types.yaml#/definitions/uint32"
  95     minimum: 0
  96     maximum: 0xf
  97
  98   ti,otap-del-sel-ddr50:
  99     description: Output tap delay for SD UHS DDR50 timing
 100     $ref: "/schemas/types.yaml#/definitions/uint32"
 101     minimum: 0
 102     maximum: 0xf
 103
 104   ti,otap-del-sel-ddr52:
 105     description: Output tap delay for eMMC DDR52 timing
 106     $ref: "/schemas/types.yaml#/definitions/uint32"
 107     minimum: 0
 108     maximum: 0xf
 109
 110   ti,otap-del-sel-hs200:
 111     description: Output tap delay for eMMC HS200 timing
 112     $ref: "/schemas/types.yaml#/definitions/uint32"
 113     minimum: 0
 114     maximum: 0xf
 115
 116   ti,otap-del-sel-hs400:
 117     description: Output tap delay for eMMC HS400 timing
 118     $ref: "/schemas/types.yaml#/definitions/uint32"
 119     minimum: 0
 120     maximum: 0xf
 121
 122   # PHY input tap delays:
 123   # Used to delay the data valid window and align it to the sampling clock for
 124   # modes that don't support tuning
 125
 126   ti,itap-del-sel-legacy:
 127     description: Input tap delay for SD/MMC legacy timing
 128     $ref: "/schemas/types.yaml#/definitions/uint32"
 129     minimum: 0
 130     maximum: 0x1f
 131
 132   ti,itap-del-sel-mmc-hs:
 133     description: Input tap delay for MMC high speed timing
 134     $ref: "/schemas/types.yaml#/definitions/uint32"
 135     minimum: 0
 136     maximum: 0x1f
 137
 138   ti,itap-del-sel-sd-hs:
 139     description: Input tap delay for SD high speed timing
 140     $ref: "/schemas/types.yaml#/definitions/uint32"
 141     minimum: 0
 142     maximum: 0x1f
 143
 144   ti,itap-del-sel-sdr12:
 145     description: Input tap delay for SD UHS SDR12 timing
 146     $ref: "/schemas/types.yaml#/definitions/uint32"
 147     minimum: 0
 148     maximum: 0x1f
 149
 150   ti,itap-del-sel-sdr25:
 151     description: Input tap delay for SD UHS SDR25 timing
 152     $ref: "/schemas/types.yaml#/definitions/uint32"
 153     minimum: 0
 154     maximum: 0x1f
 155
 156   ti,itap-del-sel-ddr52:
 157     description: Input tap delay for MMC DDR52 timing
 158     $ref: "/schemas/types.yaml#/definitions/uint32"
 159     minimum: 0
 160     maximum: 0x1f
 161
 162   ti,trm-icp:
 163     description: DLL trim select
 164     $ref: "/schemas/types.yaml#/definitions/uint32"
 165     minimum: 0
 166     maximum: 0xf
 167
 168   ti,driver-strength-ohm:
 169     description: DLL drive strength in ohms
 170     $ref: "/schemas/types.yaml#/definitions/uint32"
 171     enum:
 172       - 33
 173       - 40
 174       - 50
 175       - 66
 176       - 100
 177
 178   ti,strobe-sel:
 179     description: strobe select delay for HS400 speed mode.
 180     $ref: "/schemas/types.yaml#/definitions/uint32"
 181
 182   ti,clkbuf-sel:
 183     description: Clock Delay Buffer Select
 184     $ref: "/schemas/types.yaml#/definitions/uint32"
 185
 186 required:
 187   - compatible
 188   - reg
 189   - interrupts
 190   - clocks
 191   - clock-names
 192   - ti,otap-del-sel-legacy
 193
 194 unevaluatedProperties: false
 195
 196 examples:
 197   - |
 198     #include <dt-bindings/interrupt-controller/irq.h>
 199     #include <dt-bindings/interrupt-controller/arm-gic.h>
 200
 201     bus {
 202         #address-cells = <2>;
 203         #size-cells = <2>;
 204
 205         mmc0: mmc@4f80000 {
 206             compatible = "ti,am654-sdhci-5.1";
 207             reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
 208             power-domains = <&k3_pds 47>;
 209             clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
 210             clock-names = "clk_ahb", "clk_xin";
 211             interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
 212             sdhci-caps-mask = <0x80000007 0x0>;
 213             mmc-ddr-1_8v;
 214             ti,otap-del-sel-legacy = <0x0>;
 215             ti,otap-del-sel-mmc-hs = <0x0>;
 216             ti,otap-del-sel-ddr52 = <0x5>;
 217             ti,otap-del-sel-hs200 = <0x5>;
 218             ti,otap-del-sel-hs400 = <0x0>;
 219             ti,itap-del-sel-legacy = <0x10>;
 220             ti,itap-del-sel-mmc-hs = <0xa>;
 221             ti,itap-del-sel-ddr52 = <0x3>;
 222             ti,trm-icp = <0x8>;
 223         };
 224     };