Merge commit '81fd23e2b3ccf71c807e671444e8accaba98ca53' of https://git.pengutronix...
[linux-2.6-microblaze.git] / Documentation / devicetree / bindings / mmc / rockchip-dw-mshc.yaml
1 # SPDX-License-Identifier: GPL-2.0
2 %YAML 1.2
3 ---
4 $id: http://devicetree.org/schemas/mmc/rockchip-dw-mshc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
6
7 title: Rockchip designware mobile storage host controller device tree bindings
8
9 description:
10   Rockchip uses the Synopsys designware mobile storage host controller
11   to interface a SoC with storage medium such as eMMC or SD/MMC cards.
12   This file documents the combined properties for the core Synopsys dw mshc
13   controller that are not already included in the synopsys-dw-mshc-common.yaml
14   file and the Rockchip specific extensions.
15
16 allOf:
17   - $ref: "synopsys-dw-mshc-common.yaml#"
18
19 maintainers:
20   - Heiko Stuebner <heiko@sntech.de>
21
22 # Everything else is described in the common file
23 properties:
24   compatible:
25     oneOf:
26       # for Rockchip RK2928 and before RK3288
27       - const: rockchip,rk2928-dw-mshc
28       # for Rockchip RK3288
29       - const: rockchip,rk3288-dw-mshc
30       - items:
31           - enum:
32               - rockchip,px30-dw-mshc
33               - rockchip,rk1808-dw-mshc
34               - rockchip,rk3036-dw-mshc
35               - rockchip,rk3228-dw-mshc
36               - rockchip,rk3308-dw-mshc
37               - rockchip,rk3328-dw-mshc
38               - rockchip,rk3368-dw-mshc
39               - rockchip,rk3399-dw-mshc
40               - rockchip,rk3568-dw-mshc
41               - rockchip,rv1108-dw-mshc
42           - const: rockchip,rk3288-dw-mshc
43
44   reg:
45     maxItems: 1
46
47   interrupts:
48     maxItems: 1
49
50   clocks:
51     minItems: 2
52     maxItems: 4
53     description:
54       Handle to "biu" and "ciu" clocks for the bus interface unit clock and
55       the card interface unit clock. If "ciu-drive" and "ciu-sample" are
56       specified in clock-names, it should also contain
57       handles to these clocks.
58
59   clock-names:
60     minItems: 2
61     items:
62       - const: biu
63       - const: ciu
64       - const: ciu-drive
65       - const: ciu-sample
66     description:
67       Apart from the clock-names "biu" and "ciu" two more clocks
68       "ciu-drive" and "ciu-sample" are supported. They are used
69       to control the clock phases, "ciu-sample" is required for tuning
70       high speed modes.
71
72   rockchip,default-sample-phase:
73     $ref: /schemas/types.yaml#/definitions/uint32
74     minimum: 0
75     maximum: 360
76     default: 0
77     description:
78       The default phase to set "ciu-sample" at probing,
79       low speeds or in case where all phases work at tuning time.
80       If not specified 0 deg will be used.
81
82   rockchip,desired-num-phases:
83     $ref: /schemas/types.yaml#/definitions/uint32
84     minimum: 0
85     maximum: 360
86     default: 360
87     description:
88       The desired number of times that the host execute tuning when needed.
89       If not specified, the host will do tuning for 360 times,
90       namely tuning for each degree.
91
92 required:
93   - compatible
94   - reg
95   - interrupts
96   - clocks
97   - clock-names
98
99 unevaluatedProperties: false
100
101 examples:
102   - |
103     #include <dt-bindings/clock/rk3288-cru.h>
104     #include <dt-bindings/interrupt-controller/arm-gic.h>
105     #include <dt-bindings/interrupt-controller/irq.h>
106     sdmmc: mmc@ff0c0000 {
107       compatible = "rockchip,rk3288-dw-mshc";
108       reg = <0xff0c0000 0x4000>;
109       interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
110       clocks = <&cru HCLK_SDMMC>, <&cru SCLK_SDMMC>,
111                <&cru SCLK_SDMMC_DRV>, <&cru SCLK_SDMMC_SAMPLE>;
112       clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
113       resets = <&cru SRST_MMC0>;
114       reset-names = "reset";
115       fifo-depth = <0x100>;
116       max-frequency = <150000000>;
117     };
118
119 ...