1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
4 $id: "http://devicetree.org/schemas/mmc/renesas,sdhi.yaml#"
5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
7 title: Renesas SDHI SD/MMC controller
10 - Wolfram Sang <wsa+renesas@sang-engineering.com>
13 - $ref: "mmc-controller.yaml"
19 - const: renesas,sdhi-sh73a0 # R-Mobile APE6
21 - const: renesas,sdhi-r7s72100 # RZ/A1H
23 - const: renesas,sdhi-r7s9210 # SH-Mobile AG5
25 - const: renesas,sdhi-r8a73a4 # R-Mobile APE6
27 - const: renesas,sdhi-r8a7740 # R-Mobile A1
30 - renesas,sdhi-r8a7778 # R-Car M1
31 - renesas,sdhi-r8a7779 # R-Car H1
32 - const: renesas,rcar-gen1-sdhi # R-Car Gen1
35 - renesas,sdhi-r8a7742 # RZ/G1H
36 - renesas,sdhi-r8a7743 # RZ/G1M
37 - renesas,sdhi-r8a7744 # RZ/G1N
38 - renesas,sdhi-r8a7745 # RZ/G1E
39 - renesas,sdhi-r8a77470 # RZ/G1C
40 - renesas,sdhi-r8a7790 # R-Car H2
41 - renesas,sdhi-r8a7791 # R-Car M2-W
42 - renesas,sdhi-r8a7792 # R-Car V2H
43 - renesas,sdhi-r8a7793 # R-Car M2-N
44 - renesas,sdhi-r8a7794 # R-Car E2
45 - const: renesas,rcar-gen2-sdhi # R-Car Gen2 and RZ/G1
47 - const: renesas,sdhi-mmc-r8a77470 # RZ/G1C (SDHI/MMC IP)
50 - renesas,sdhi-r8a774a1 # RZ/G2M
51 - renesas,sdhi-r8a774b1 # RZ/G2N
52 - renesas,sdhi-r8a774c0 # RZ/G2E
53 - renesas,sdhi-r8a774e1 # RZ/G2H
54 - renesas,sdhi-r8a7795 # R-Car H3
55 - renesas,sdhi-r8a7796 # R-Car M3-W
56 - renesas,sdhi-r8a77961 # R-Car M3-W+
57 - renesas,sdhi-r8a77965 # R-Car M3-N
58 - renesas,sdhi-r8a77970 # R-Car V3M
59 - renesas,sdhi-r8a77980 # R-Car V3H
60 - renesas,sdhi-r8a77990 # R-Car E3
61 - renesas,sdhi-r8a77995 # R-Car D3
62 - renesas,sdhi-r8a779a0 # R-Car V3U
63 - const: renesas,rcar-gen3-sdhi # R-Car Gen3 or RZ/G2
127 - renesas,sdhi-r7s72100
128 - renesas,sdhi-r7s9210
133 The internal card detection logic that exists in these controllers is
134 sectioned off to be run by a separate second clock source to allow
135 the main core clock to be turned off to save power.
137 unevaluatedProperties: false
141 #include <dt-bindings/clock/r8a7790-cpg-mssr.h>
142 #include <dt-bindings/interrupt-controller/arm-gic.h>
143 #include <dt-bindings/power/r8a7790-sysc.h>
145 sdhi0: mmc@ee100000 {
146 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
147 reg = <0xee100000 0x328>;
148 interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
149 clocks = <&cpg CPG_MOD 314>;
150 dmas = <&dmac0 0xcd>, <&dmac0 0xce>, <&dmac1 0xcd>, <&dmac1 0xce>;
151 dma-names = "tx", "rx", "tx", "rx";
152 max-frequency = <195000000>;
153 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
157 sdhi1: mmc@ee120000 {
158 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
159 reg = <0xee120000 0x328>;
160 interrupts = <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>;
161 clocks = <&cpg CPG_MOD 313>;
162 dmas = <&dmac0 0xc9>, <&dmac0 0xca>, <&dmac1 0xc9>, <&dmac1 0xca>;
163 dma-names = "tx", "rx", "tx", "rx";
164 max-frequency = <195000000>;
165 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
169 sdhi2: mmc@ee140000 {
170 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
171 reg = <0xee140000 0x100>;
172 interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
173 clocks = <&cpg CPG_MOD 312>;
174 dmas = <&dmac0 0xc1>, <&dmac0 0xc2>, <&dmac1 0xc1>, <&dmac1 0xc2>;
175 dma-names = "tx", "rx", "tx", "rx";
176 max-frequency = <97500000>;
177 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;
181 sdhi3: mmc@ee160000 {
182 compatible = "renesas,sdhi-r8a7790", "renesas,rcar-gen2-sdhi";
183 reg = <0xee160000 0x100>;
184 interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
185 clocks = <&cpg CPG_MOD 311>;
186 dmas = <&dmac0 0xd3>, <&dmac0 0xd4>, <&dmac1 0xd3>, <&dmac1 0xd4>;
187 dma-names = "tx", "rx", "tx", "rx";
188 max-frequency = <97500000>;
189 power-domains = <&sysc R8A7790_PD_ALWAYS_ON>;