1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/mmc/mtk-sd.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
7 title: MTK MSDC Storage Host Controller Binding
10 - Chaotian Jing <chaotian.jing@mediatek.com>
11 - Wenbin Mei <wenbin.mei@mediatek.com>
14 - $ref: mmc-controller.yaml#
30 - const: mediatek,mt7623-mmc
31 - const: mediatek,mt2701-mmc
33 - const: mediatek,mt8192-mmc
34 - const: mediatek,mt8183-mmc
38 Should contain phandle for the clock feeding the MMC controller.
42 - description: source clock (required).
43 - description: HCLK which used for host (required).
44 - description: independent source clock gate (required for MT2712).
45 - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
46 - description: msdc subsys clock gate (required for MT8192).
47 - description: peripheral bus clock gate (required for MT8192).
48 - description: AXI bus clock gate (required for MT8192).
49 - description: AHB bus clock gate (required for MT8192).
71 should contain default/high speed pin ctrl.
76 should contain uhs mode pin ctrl.
81 PLL of the source clock.
84 assigned-clock-parents:
86 parent of source clock, used for HS400 mode to get 400Mhz source clock.
90 $ref: /schemas/types.yaml#/definitions/uint32
92 HS400 DS delay setting.
96 mediatek,hs200-cmd-int-delay:
97 $ref: /schemas/types.yaml#/definitions/uint32
99 HS200 command internal delay setting.
100 This field has total 32 stages.
101 The value is an integer from 0 to 31.
105 mediatek,hs400-cmd-int-delay:
106 $ref: /schemas/types.yaml#/definitions/uint32
108 HS400 command internal delay setting.
109 This field has total 32 stages.
110 The value is an integer from 0 to 31.
114 mediatek,hs400-cmd-resp-sel-rising:
115 $ref: /schemas/types.yaml#/definitions/flag
117 HS400 command response sample selection.
118 If present, HS400 command responses are sampled on rising edges.
119 If not present, HS400 command responses are sampled on falling edges.
122 $ref: /schemas/types.yaml#/definitions/uint32
124 Some SoCs do not support enhance_rx, need set correct latch-ck to avoid
125 data crc error caused by stop clock(fifo full) Valid range = [0:0x7].
126 if not present, default value is 0.
127 applied to compatible "mediatek,mt2701-mmc".
149 unevaluatedProperties: false
153 #include <dt-bindings/interrupt-controller/irq.h>
154 #include <dt-bindings/interrupt-controller/arm-gic.h>
155 #include <dt-bindings/clock/mt8173-clk.h>
157 compatible = "mediatek,mt8173-mmc";
158 reg = <0x11230000 0x1000>;
159 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
160 vmmc-supply = <&mt6397_vemc_3v3_reg>;
161 vqmmc-supply = <&mt6397_vio18_reg>;
162 clocks = <&pericfg CLK_PERI_MSDC30_0>,
163 <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
164 clock-names = "source", "hclk";
165 pinctrl-names = "default", "state_uhs";
166 pinctrl-0 = <&mmc0_pins_default>;
167 pinctrl-1 = <&mmc0_pins_uhs>;
168 assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
169 assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
170 hs400-ds-delay = <0x14015>;
171 mediatek,hs200-cmd-int-delay = <26>;
172 mediatek,hs400-cmd-int-delay = <14>;
173 mediatek,hs400-cmd-resp-sel-rising;