Documentation/devicetree/bindings/mmc/arasan,sdhci.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: "http://devicetree.org/schemas/mmc/arasan,sdhci.yaml#"
   5 $schema: "http://devicetree.org/meta-schemas/core.yaml#"
   6
   7 title: Device Tree Bindings for the Arasan SDHCI Controller
   8
   9 maintainers:
  10   - Adrian Hunter <adrian.hunter@intel.com>
  11
  12 allOf:
  13   - $ref: "mmc-controller.yaml#"
  14   - if:
  15       properties:
  16         compatible:
  17           contains:
  18             const: arasan,sdhci-5.1
  19     then:
  20       required:
  21         - phys
  22         - phy-names
  23   - if:
  24       properties:
  25         compatible:
  26           contains:
  27             enum:
  28               - xlnx,zynqmp-8.9a
  29               - xlnx,versal-8.9a
  30     then:
  31       properties:
  32         clock-output-names:
  33           oneOf:
  34             - items:
  35                 - const: clk_out_sd0
  36                 - const: clk_in_sd0
  37             - items:
  38                 - const: clk_out_sd1
  39                 - const: clk_in_sd1
  40
  41 properties:
  42   compatible:
  43     oneOf:
  44       - const: arasan,sdhci-8.9a                # generic Arasan SDHCI 8.9a PHY
  45       - const: arasan,sdhci-4.9a                # generic Arasan SDHCI 4.9a PHY
  46       - const: arasan,sdhci-5.1                 # generic Arasan SDHCI 5.1 PHY
  47       - items:
  48           - const: rockchip,rk3399-sdhci-5.1    # rk3399 eMMC PHY
  49           - const: arasan,sdhci-5.1
  50         description:
  51           For this device it is strongly suggested to include
  52           arasan,soc-ctl-syscon.
  53       - items:
  54           - const: xlnx,zynqmp-8.9a             # ZynqMP SDHCI 8.9a PHY
  55           - const: arasan,sdhci-8.9a
  56         description:
  57           For this device it is strongly suggested to include
  58           clock-output-names and '#clock-cells'.
  59       - items:
  60           - const: xlnx,versal-8.9a             # Versal SDHCI 8.9a PHY
  61           - const: arasan,sdhci-8.9a
  62         description:
  63           For this device it is strongly suggested to include
  64           clock-output-names and '#clock-cells'.
  65       - items:
  66           - const: intel,lgm-sdhci-5.1-emmc     # Intel LGM eMMC PHY
  67           - const: arasan,sdhci-5.1
  68         description:
  69           For this device it is strongly suggested to include
  70           arasan,soc-ctl-syscon.
  71       - items:
  72           - const: intel,lgm-sdhci-5.1-sdxc     # Intel LGM SDXC PHY
  73           - const: arasan,sdhci-5.1
  74         description:
  75           For this device it is strongly suggested to include
  76           arasan,soc-ctl-syscon.
  77       - items:
  78           - const: intel,keembay-sdhci-5.1-emmc # Intel Keem Bay eMMC PHY
  79           - const: arasan,sdhci-5.1
  80         description:
  81           For this device it is strongly suggested to include
  82           arasan,soc-ctl-syscon.
  83       - const: intel,keembay-sdhci-5.1-sd       # Intel Keem Bay SD controller
  84         description:
  85           For this device it is strongly suggested to include
  86           arasan,soc-ctl-syscon.
  87       - const: intel,keembay-sdhci-5.1-sdio     # Intel Keem Bay SDIO controller
  88         description:
  89           For this device it is strongly suggested to include
  90           arasan,soc-ctl-syscon.
  91
  92   reg:
  93     maxItems: 1
  94
  95   clocks:
  96     minItems: 2
  97     maxItems: 3
  98
  99   clock-names:
 100     minItems: 2
 101     items:
 102       - const: clk_xin
 103       - const: clk_ahb
 104       - const: gate
 105
 106   interrupts:
 107     maxItems: 1
 108
 109   phys:
 110     maxItems: 1
 111
 112   phy-names:
 113     const: phy_arasan
 114
 115   arasan,soc-ctl-syscon:
 116     $ref: /schemas/types.yaml#/definitions/phandle
 117     description:
 118       A phandle to a syscon device (see ../mfd/syscon.txt) used to access
 119       core corecfg registers. Offsets of registers in this syscon are
 120       determined based on the main compatible string for the device.
 121
 122   clock-output-names:
 123     minItems: 1
 124     maxItems: 2
 125     description:
 126       Name of the card clock which will be exposed by this device.
 127
 128   '#clock-cells':
 129     enum: [0, 1]
 130     description:
 131       With this property in place we will export one or two clocks
 132       representing the Card Clock. These clocks are expected to be
 133       consumed by our PHY.
 134
 135   xlnx,fails-without-test-cd:
 136     $ref: /schemas/types.yaml#/definitions/flag
 137     description:
 138       When present, the controller doesn't work when the CD line is not
 139       connected properly, and the line is not connected properly.
 140       Test mode can be used to force the controller to function.
 141
 142   xlnx,int-clock-stable-broken:
 143     $ref: /schemas/types.yaml#/definitions/flag
 144     description:
 145       When present, the controller always reports that the internal clock
 146       is stable even when it is not.
 147
 148   xlnx,mio-bank:
 149     $ref: /schemas/types.yaml#/definitions/uint32
 150     enum: [0, 1, 2]
 151     default: 0
 152     description:
 153       The MIO bank number in which the command and data lines are configured.
 154
 155 dependencies:
 156   clock-output-names: [ '#clock-cells' ]
 157   '#clock-cells': [ clock-output-names ]
 158
 159 required:
 160   - compatible
 161   - reg
 162   - interrupts
 163   - clocks
 164   - clock-names
 165
 166 unevaluatedProperties: false
 167
 168 examples:
 169   - |
 170     mmc@e0100000 {
 171           compatible = "arasan,sdhci-8.9a";
 172           reg = <0xe0100000 0x1000>;
 173           clock-names = "clk_xin", "clk_ahb";
 174           clocks = <&clkc 21>, <&clkc 32>;
 175           interrupt-parent = <&gic>;
 176           interrupts = <0 24 4>;
 177     };
 178
 179   - |
 180     mmc@e2800000 {
 181           compatible = "arasan,sdhci-5.1";
 182           reg = <0xe2800000 0x1000>;
 183           clock-names = "clk_xin", "clk_ahb";
 184           clocks = <&cru 8>, <&cru 18>;
 185           interrupt-parent = <&gic>;
 186           interrupts = <0 24 4>;
 187           phys = <&emmc_phy>;
 188           phy-names = "phy_arasan";
 189     };
 190
 191   - |
 192     #include <dt-bindings/clock/rk3399-cru.h>
 193     #include <dt-bindings/interrupt-controller/arm-gic.h>
 194     #include <dt-bindings/interrupt-controller/irq.h>
 195     mmc@fe330000 {
 196           compatible = "rockchip,rk3399-sdhci-5.1", "arasan,sdhci-5.1";
 197           reg = <0xfe330000 0x10000>;
 198           interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
 199           clocks = <&cru SCLK_EMMC>, <&cru ACLK_EMMC>;
 200           clock-names = "clk_xin", "clk_ahb";
 201           arasan,soc-ctl-syscon = <&grf>;
 202           assigned-clocks = <&cru SCLK_EMMC>;
 203           assigned-clock-rates = <200000000>;
 204           clock-output-names = "emmc_cardclock";
 205           phys = <&emmc_phy>;
 206           phy-names = "phy_arasan";
 207           #clock-cells = <0>;
 208     };
 209
 210   - |
 211     mmc@ff160000 {
 212           compatible = "xlnx,zynqmp-8.9a", "arasan,sdhci-8.9a";
 213           interrupt-parent = <&gic>;
 214           interrupts = <0 48 4>;
 215           reg = <0xff160000 0x1000>;
 216           clocks = <&clk200>, <&clk200>;
 217           clock-names = "clk_xin", "clk_ahb";
 218           clock-output-names = "clk_out_sd0", "clk_in_sd0";
 219           #clock-cells = <1>;
 220           clk-phase-sd-hs = <63>, <72>;
 221     };
 222
 223   - |
 224     mmc@f1040000 {
 225           compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
 226           interrupt-parent = <&gic>;
 227           interrupts = <0 126 4>;
 228           reg = <0xf1040000 0x10000>;
 229           clocks = <&clk200>, <&clk200>;
 230           clock-names = "clk_xin", "clk_ahb";
 231           clock-output-names = "clk_out_sd0", "clk_in_sd0";
 232           #clock-cells = <1>;
 233           clk-phase-sd-hs = <132>, <60>;
 234     };
 235
 236   - |
 237     #define LGM_CLK_EMMC5
 238     #define LGM_CLK_NGI
 239     #define LGM_GCLK_EMMC
 240     mmc@ec700000 {
 241           compatible = "intel,lgm-sdhci-5.1-emmc", "arasan,sdhci-5.1";
 242           reg = <0xec700000 0x300>;
 243           interrupt-parent = <&ioapic1>;
 244           interrupts = <44 1>;
 245           clocks = <&cgu0 LGM_CLK_EMMC5>, <&cgu0 LGM_CLK_NGI>,
 246                    <&cgu0 LGM_GCLK_EMMC>;
 247           clock-names = "clk_xin", "clk_ahb", "gate";
 248           clock-output-names = "emmc_cardclock";
 249           #clock-cells = <0>;
 250           phys = <&emmc_phy>;
 251           phy-names = "phy_arasan";
 252           arasan,soc-ctl-syscon = <&sysconf>;
 253     };
 254
 255   - |
 256     #define LGM_CLK_SDIO
 257     #define LGM_GCLK_SDXC
 258     mmc@ec600000 {
 259           compatible = "intel,lgm-sdhci-5.1-sdxc", "arasan,sdhci-5.1";
 260           reg = <0xec600000 0x300>;
 261           interrupt-parent = <&ioapic1>;
 262           interrupts = <43 1>;
 263           clocks = <&cgu0 LGM_CLK_SDIO>, <&cgu0 LGM_CLK_NGI>,
 264                    <&cgu0 LGM_GCLK_SDXC>;
 265           clock-names = "clk_xin", "clk_ahb", "gate";
 266           clock-output-names = "sdxc_cardclock";
 267           #clock-cells = <0>;
 268           phys = <&sdxc_phy>;
 269           phy-names = "phy_arasan";
 270           arasan,soc-ctl-syscon = <&sysconf>;
 271     };
 272
 273   - |
 274     #define KEEM_BAY_PSS_AUX_EMMC
 275     #define KEEM_BAY_PSS_EMMC
 276     mmc@33000000 {
 277           compatible = "intel,keembay-sdhci-5.1-emmc", "arasan,sdhci-5.1";
 278           interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 279           reg = <0x33000000 0x300>;
 280           clock-names = "clk_xin", "clk_ahb";
 281           clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>,
 282                    <&scmi_clk KEEM_BAY_PSS_EMMC>;
 283           phys = <&emmc_phy>;
 284           phy-names = "phy_arasan";
 285           assigned-clocks = <&scmi_clk KEEM_BAY_PSS_AUX_EMMC>;
 286           assigned-clock-rates = <200000000>;
 287           clock-output-names = "emmc_cardclock";
 288           #clock-cells = <0>;
 289           arasan,soc-ctl-syscon = <&mmc_phy_syscon>;
 290     };
 291
 292   - |
 293     #define KEEM_BAY_PSS_AUX_SD0
 294     #define KEEM_BAY_PSS_SD0
 295     mmc@31000000 {
 296           compatible = "intel,keembay-sdhci-5.1-sd";
 297           interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
 298           reg = <0x31000000 0x300>;
 299           clock-names = "clk_xin", "clk_ahb";
 300           clocks = <&scmi_clk KEEM_BAY_PSS_AUX_SD0>,
 301                    <&scmi_clk KEEM_BAY_PSS_SD0>;
 302           arasan,soc-ctl-syscon = <&sd0_phy_syscon>;
 303     };