Documentation/devicetree/bindings/memory-controllers/synopsys,ddrc-ecc.yaml

   1 # SPDX-License-Identifier: GPL-2.0-only
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/synopsys,ddrc-ecc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: Synopsys IntelliDDR Multi Protocol memory controller
   8
   9 maintainers:
  10   - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
  11   - Manish Narani <manish.narani@xilinx.com>
  12   - Michal Simek <michal.simek@xilinx.com>
  13
  14 description: |
  15   The ZynqMP DDR ECC controller has an optional ECC support in 64-bit and
  16   32-bit bus width configurations.
  17
  18   The Zynq DDR ECC controller has an optional ECC support in half-bus width
  19   (16-bit) configuration.
  20
  21   These both ECC controllers correct single bit ECC errors and detect double bit
  22   ECC errors.
  23
  24 properties:
  25   compatible:
  26     enum:
  27       - xlnx,zynq-ddrc-a05
  28       - xlnx,zynqmp-ddrc-2.40a
  29
  30   interrupts:
  31     maxItems: 1
  32
  33   reg:
  34     maxItems: 1
  35
  36 required:
  37   - compatible
  38   - reg
  39
  40 allOf:
  41   - if:
  42       properties:
  43         compatible:
  44           contains:
  45             const: xlnx,zynqmp-ddrc-2.40a
  46     then:
  47       required:
  48         - interrupts
  49     else:
  50       properties:
  51         interrupts: false
  52
  53 additionalProperties: false
  54
  55 examples:
  56   - |
  57     memory-controller@f8006000 {
  58         compatible = "xlnx,zynq-ddrc-a05";
  59         reg = <0xf8006000 0x1000>;
  60     };
  61
  62   - |
  63     axi {
  64         #address-cells = <2>;
  65         #size-cells = <2>;
  66
  67         memory-controller@fd070000 {
  68             compatible = "xlnx,zynqmp-ddrc-2.40a";
  69             reg = <0x0 0xfd070000 0x0 0x30000>;
  70             interrupt-parent = <&gic>;
  71             interrupts = <0 112 4>;
  72         };
  73     };