1 # SPDX-License-Identifier: GPL-2.0
4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
5 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
12 - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
13 - Lukasz Luba <lukasz.luba@arm.com>
16 The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
17 DRAM memory chips are connected. The driver is to monitor the controller in
18 runtime and switch frequency and voltage. To monitor the usage of the
19 controller in runtime, the driver uses the PPMU (Platform Performance
20 Monitoring Unit), which is able to measure the current load of the memory.
21 When 'userspace' governor is used for the driver, an application is able to
22 switch the DMC and memory frequency.
27 - const: samsung,exynos5422-dmc
32 - const: mout_sclk_spll
33 - const: ff_dout_spll2
37 - const: mout_mx_mspll_ccore
38 - const: mout_mclk_cdrex
45 $ref: '/schemas/types.yaml#/definitions/phandle-array'
48 description: phandles of the PPMU events used by the controller.
51 $ref: '/schemas/types.yaml#/definitions/phandle'
53 phandle of the connected DRAM memory device. For more information please
54 refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
56 operating-points-v2: true
60 - description: DMC internal performance event counters in DREX0
61 - description: DMC internal performance event counters in DREX1
70 - description: registers of DREX0
71 - description: registers of DREX1
74 $ref: '/schemas/types.yaml#/definitions/phandle'
76 Phandle of the clock register set used by the controller, these registers
77 are used for enabling a 'pause' feature and are not exposed by clock
78 framework but they must be used in a safe way. The register offsets are
79 in the driver code and specyfic for this SoC type.
92 additionalProperties: false
96 #include <dt-bindings/clock/exynos5420.h>
97 ppmu_dmc0_0: ppmu@10d00000 {
98 compatible = "samsung,exynos-ppmu";
99 reg = <0x10d00000 0x2000>;
100 clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
101 clock-names = "ppmu";
103 ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
104 event-name = "ppmu-event3-dmc0_0";
109 memory-controller@10c20000 {
110 compatible = "samsung,exynos5422-dmc";
111 reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
112 clocks = <&clock CLK_FOUT_SPLL>,
113 <&clock CLK_MOUT_SCLK_SPLL>,
114 <&clock CLK_FF_DOUT_SPLL2>,
115 <&clock CLK_FOUT_BPLL>,
116 <&clock CLK_MOUT_BPLL>,
117 <&clock CLK_SCLK_BPLL>,
118 <&clock CLK_MOUT_MX_MSPLL_CCORE>,
119 <&clock CLK_MOUT_MCLK_CDREX>;
120 clock-names = "fout_spll",
126 "mout_mx_mspll_ccore",
128 operating-points-v2 = <&dmc_opp_table>;
129 devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
130 <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
131 device-handle = <&samsung_K3QF2F20DB>;
132 vdd-supply = <&buck1_reg>;
133 samsung,syscon-clk = <&clock>;
134 interrupt-parent = <&combiner>;
135 interrupts = <16 0>, <16 1>;
136 interrupt-names = "drex_0", "drex_1";