Documentation/devicetree/bindings/memory-controllers/samsung,exynos5422-dmc.yaml

   1 # SPDX-License-Identifier: GPL-2.0
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/samsung,exynos5422-dmc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: |
   8   Samsung Exynos5422 SoC frequency and voltage scaling for Dynamic Memory
   9   Controller device
  10
  11 maintainers:
  12   - Krzysztof Kozlowski <krzysztof.kozlowski@canonical.com>
  13   - Lukasz Luba <lukasz.luba@arm.com>
  14
  15 description: |
  16   The Samsung Exynos5422 SoC has DMC (Dynamic Memory Controller) to which the
  17   DRAM memory chips are connected. The driver is to monitor the controller in
  18   runtime and switch frequency and voltage. To monitor the usage of the
  19   controller in runtime, the driver uses the PPMU (Platform Performance
  20   Monitoring Unit), which is able to measure the current load of the memory.
  21   When 'userspace' governor is used for the driver, an application is able to
  22   switch the DMC and memory frequency.
  23
  24 properties:
  25   compatible:
  26     items:
  27       - const: samsung,exynos5422-dmc
  28
  29   clock-names:
  30     items:
  31       - const: fout_spll
  32       - const: mout_sclk_spll
  33       - const: ff_dout_spll2
  34       - const: fout_bpll
  35       - const: mout_bpll
  36       - const: sclk_bpll
  37       - const: mout_mx_mspll_ccore
  38       - const: mout_mclk_cdrex
  39
  40   clocks:
  41     minItems: 8
  42     maxItems: 8
  43
  44   devfreq-events:
  45     $ref: '/schemas/types.yaml#/definitions/phandle-array'
  46     minItems: 1
  47     maxItems: 16
  48     description: phandles of the PPMU events used by the controller.
  49
  50   device-handle:
  51     $ref: '/schemas/types.yaml#/definitions/phandle'
  52     description: |
  53       phandle of the connected DRAM memory device. For more information please
  54       refer to documentation file: Documentation/devicetree/bindings/ddr/lpddr3.txt
  55
  56   operating-points-v2: true
  57
  58   interrupts:
  59     items:
  60       - description: DMC internal performance event counters in DREX0
  61       - description: DMC internal performance event counters in DREX1
  62
  63   interrupt-names:
  64     items:
  65       - const: drex_0
  66       - const: drex_1
  67
  68   reg:
  69     items:
  70       - description: registers of DREX0
  71       - description: registers of DREX1
  72
  73   samsung,syscon-clk:
  74     $ref: '/schemas/types.yaml#/definitions/phandle'
  75     description: |
  76       Phandle of the clock register set used by the controller, these registers
  77       are used for enabling a 'pause' feature and are not exposed by clock
  78       framework but they must be used in a safe way.  The register offsets are
  79       in the driver code and specyfic for this SoC type.
  80
  81   vdd-supply: true
  82
  83 required:
  84   - compatible
  85   - clock-names
  86   - clocks
  87   - devfreq-events
  88   - device-handle
  89   - reg
  90   - samsung,syscon-clk
  91
  92 additionalProperties: false
  93
  94 examples:
  95   - |
  96     #include <dt-bindings/clock/exynos5420.h>
  97     ppmu_dmc0_0: ppmu@10d00000 {
  98         compatible = "samsung,exynos-ppmu";
  99         reg = <0x10d00000 0x2000>;
 100         clocks = <&clock CLK_PCLK_PPMU_DREX0_0>;
 101         clock-names = "ppmu";
 102         events {
 103             ppmu_event_dmc0_0: ppmu-event3-dmc0-0 {
 104                 event-name = "ppmu-event3-dmc0_0";
 105             };
 106         };
 107     };
 108
 109     memory-controller@10c20000 {
 110         compatible = "samsung,exynos5422-dmc";
 111         reg = <0x10c20000 0x10000>, <0x10c30000 0x10000>;
 112         clocks = <&clock CLK_FOUT_SPLL>,
 113                  <&clock CLK_MOUT_SCLK_SPLL>,
 114                  <&clock CLK_FF_DOUT_SPLL2>,
 115                  <&clock CLK_FOUT_BPLL>,
 116                  <&clock CLK_MOUT_BPLL>,
 117                  <&clock CLK_SCLK_BPLL>,
 118                  <&clock CLK_MOUT_MX_MSPLL_CCORE>,
 119                  <&clock CLK_MOUT_MCLK_CDREX>;
 120         clock-names = "fout_spll",
 121                       "mout_sclk_spll",
 122                       "ff_dout_spll2",
 123                       "fout_bpll",
 124                       "mout_bpll",
 125                       "sclk_bpll",
 126                       "mout_mx_mspll_ccore",
 127                       "mout_mclk_cdrex";
 128         operating-points-v2 = <&dmc_opp_table>;
 129         devfreq-events = <&ppmu_event3_dmc0_0>, <&ppmu_event3_dmc0_1>,
 130                          <&ppmu_event3_dmc1_0>, <&ppmu_event3_dmc1_1>;
 131         device-handle = <&samsung_K3QF2F20DB>;
 132         vdd-supply = <&buck1_reg>;
 133         samsung,syscon-clk = <&clock>;
 134         interrupt-parent = <&combiner>;
 135         interrupts = <16 0>, <16 1>;
 136         interrupt-names = "drex_0", "drex_1";
 137     };