Documentation/devicetree/bindings/memory-controllers/nvidia,tegra20-emc.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra20-emc.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NVIDIA Tegra20 SoC External Memory Controller
   8
   9 maintainers:
  10   - Dmitry Osipenko <digetx@gmail.com>
  11   - Jon Hunter <jonathanh@nvidia.com>
  12   - Thierry Reding <thierry.reding@gmail.com>
  13
  14 description: |
  15   The External Memory Controller (EMC) interfaces with the off-chip SDRAM to
  16   service the request stream sent from Memory Controller. The EMC also has
  17   various performance-affecting settings beyond the obvious SDRAM configuration
  18   parameters and initialization settings. Tegra20 EMC supports multiple JEDEC
  19   standard protocols: DDR1, LPDDR2 and DDR2.
  20
  21 properties:
  22   compatible:
  23     const: nvidia,tegra20-emc
  24
  25   reg:
  26     maxItems: 1
  27
  28   clocks:
  29     maxItems: 1
  30
  31   interrupts:
  32     maxItems: 1
  33
  34   "#address-cells":
  35     const: 1
  36
  37   "#size-cells":
  38     const: 0
  39
  40   "#interconnect-cells":
  41     const: 0
  42
  43   nvidia,memory-controller:
  44     $ref: /schemas/types.yaml#/definitions/phandle
  45     description:
  46       Phandle of the Memory Controller node.
  47
  48   power-domains:
  49     maxItems: 1
  50     description:
  51       Phandle of the SoC "core" power domain.
  52
  53   operating-points-v2:
  54     description:
  55       Should contain freqs and voltages and opp-supported-hw property, which
  56       is a bitfield indicating SoC process ID mask.
  57
  58   nvidia,use-ram-code:
  59     type: boolean
  60     description:
  61       If present, the emc-tables@ sub-nodes will be addressed.
  62
  63 $defs:
  64   emc-table:
  65     type: object
  66     properties:
  67       compatible:
  68         const: nvidia,tegra20-emc-table
  69
  70       clock-frequency:
  71         description:
  72           Memory clock rate in kHz.
  73         minimum: 1000
  74         maximum: 900000
  75
  76       reg:
  77         maxItems: 1
  78         description:
  79           Either an opaque enumerator to tell different tables apart, or
  80           the valid frequency for which the table should be used (in kHz).
  81
  82       nvidia,emc-registers:
  83         description:
  84           EMC timing characterization data. These are the registers
  85           (see section "15.4.1 EMC Registers" in the TRM) whose values
  86           need to be specified, according to the board documentation.
  87         $ref: /schemas/types.yaml#/definitions/uint32-array
  88         items:
  89           - description: EMC_RC
  90           - description: EMC_RFC
  91           - description: EMC_RAS
  92           - description: EMC_RP
  93           - description: EMC_R2W
  94           - description: EMC_W2R
  95           - description: EMC_R2P
  96           - description: EMC_W2P
  97           - description: EMC_RD_RCD
  98           - description: EMC_WR_RCD
  99           - description: EMC_RRD
 100           - description: EMC_REXT
 101           - description: EMC_WDV
 102           - description: EMC_QUSE
 103           - description: EMC_QRST
 104           - description: EMC_QSAFE
 105           - description: EMC_RDV
 106           - description: EMC_REFRESH
 107           - description: EMC_BURST_REFRESH_NUM
 108           - description: EMC_PDEX2WR
 109           - description: EMC_PDEX2RD
 110           - description: EMC_PCHG2PDEN
 111           - description: EMC_ACT2PDEN
 112           - description: EMC_AR2PDEN
 113           - description: EMC_RW2PDEN
 114           - description: EMC_TXSR
 115           - description: EMC_TCKE
 116           - description: EMC_TFAW
 117           - description: EMC_TRPAB
 118           - description: EMC_TCLKSTABLE
 119           - description: EMC_TCLKSTOP
 120           - description: EMC_TREFBW
 121           - description: EMC_QUSE_EXTRA
 122           - description: EMC_FBIO_CFG6
 123           - description: EMC_ODT_WRITE
 124           - description: EMC_ODT_READ
 125           - description: EMC_FBIO_CFG5
 126           - description: EMC_CFG_DIG_DLL
 127           - description: EMC_DLL_XFORM_DQS
 128           - description: EMC_DLL_XFORM_QUSE
 129           - description: EMC_ZCAL_REF_CNT
 130           - description: EMC_ZCAL_WAIT_CNT
 131           - description: EMC_AUTO_CAL_INTERVAL
 132           - description: EMC_CFG_CLKTRIM_0
 133           - description: EMC_CFG_CLKTRIM_1
 134           - description: EMC_CFG_CLKTRIM_2
 135
 136     required:
 137       - clock-frequency
 138       - compatible
 139       - reg
 140       - nvidia,emc-registers
 141
 142     additionalProperties: false
 143
 144 patternProperties:
 145   "^emc-table@[0-9]+$":
 146     $ref: "#/$defs/emc-table"
 147
 148   "^emc-tables@[a-z0-9-]+$":
 149     type: object
 150     properties:
 151       reg:
 152         maxItems: 1
 153         description:
 154           An opaque enumerator to tell different tables apart.
 155
 156       nvidia,ram-code:
 157         $ref: /schemas/types.yaml#/definitions/uint32
 158         description:
 159           Value of RAM_CODE this timing set is used for.
 160
 161       "#address-cells":
 162         const: 1
 163
 164       "#size-cells":
 165         const: 0
 166
 167     patternProperties:
 168       "^emc-table@[0-9]+$":
 169         $ref: "#/$defs/emc-table"
 170
 171     required:
 172       - nvidia,ram-code
 173
 174     additionalProperties: false
 175
 176 required:
 177   - compatible
 178   - reg
 179   - interrupts
 180   - clocks
 181   - nvidia,memory-controller
 182   - "#interconnect-cells"
 183   - operating-points-v2
 184
 185 additionalProperties: false
 186
 187 examples:
 188   - |
 189     external-memory-controller@7000f400 {
 190         compatible = "nvidia,tegra20-emc";
 191         reg = <0x7000f400 0x400>;
 192         interrupts = <0 78 4>;
 193         clocks = <&clock_controller 57>;
 194
 195         nvidia,memory-controller = <&mc>;
 196         operating-points-v2 = <&dvfs_opp_table>;
 197         power-domains = <&domain>;
 198
 199         #interconnect-cells = <0>;
 200         #address-cells = <1>;
 201         #size-cells = <0>;
 202
 203         nvidia,use-ram-code;
 204
 205         emc-tables@0 {
 206             nvidia,ram-code = <0>;
 207             reg = <0>;
 208
 209             #address-cells = <1>;
 210             #size-cells = <0>;
 211
 212             emc-table@333000 {
 213                 reg = <333000>;
 214                 compatible = "nvidia,tegra20-emc-table";
 215                 clock-frequency = <333000>;
 216                 nvidia,emc-registers = <0x00000018 0x00000033
 217                         0x00000012 0x00000004 0x00000004 0x00000005
 218                         0x00000003 0x0000000c 0x00000006 0x00000006
 219                         0x00000003 0x00000001 0x00000004 0x00000005
 220                         0x00000004 0x00000009 0x0000000d 0x00000bff
 221                         0x00000000 0x00000003 0x00000003 0x00000006
 222                         0x00000006 0x00000001 0x00000011 0x000000c8
 223                         0x00000003 0x0000000e 0x00000007 0x00000008
 224                         0x00000002 0x00000000 0x00000000 0x00000002
 225                         0x00000000 0x00000000 0x00000083 0xf0440303
 226                         0x007fe010 0x00001414 0x00000000 0x00000000
 227                         0x00000000 0x00000000 0x00000000 0x00000000>;
 228             };
 229         };
 230     };