1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2 # Copyright (c) 2020 MediaTek Inc.
5 $id: http://devicetree.org/schemas/memory-controllers/mediatek,smi-common.yaml#
6 $schema: http://devicetree.org/meta-schemas/core.yaml#
8 title: SMI (Smart Multimedia Interface) Common
11 - Yong Wu <yong.wu@mediatek.com>
14 The hardware block diagram please check bindings/iommu/mediatek,iommu.yaml
16 MediaTek SMI have two generations of HW architecture, here is the list
17 which generation the SoCs use:
18 generation 1: mt2701 and mt7623.
19 generation 2: mt2712, mt6779, mt8167, mt8173, mt8183 and mt8192.
21 There's slight differences between the two SMI, for generation 2, the
22 register which control the iommu port is at each larb's register base. But
23 for generation 1, the register is at smi ao base(smi always on register
24 base). Besides that, the smi async clock should be prepared and enabled for
25 SMI generation 1 to transform the smi clock into emi clock domain, but that is
26 not needed for SMI generation 2.
32 - mediatek,mt2701-smi-common
33 - mediatek,mt2712-smi-common
34 - mediatek,mt6779-smi-common
35 - mediatek,mt8167-smi-common
36 - mediatek,mt8173-smi-common
37 - mediatek,mt8183-smi-common
38 - mediatek,mt8192-smi-common
40 - description: for mt7623
42 - const: mediatek,mt7623-smi-common
43 - const: mediatek,mt2701-smi-common
53 apb and smi are mandatory. the async is only for generation 1 smi HW.
54 gals(global async local sync) also is optional, see below.
57 - description: apb is Advanced Peripheral Bus clock, It's the clock for
59 - description: smi is the clock for transfer data and command.
60 - description: Either asynchronous clock to help transform the smi clock
61 into the emi clock domain on Gen1 h/w, or the path0 clock of gals.
62 - description: gals1 is the path1 clock of gals.
76 - if: # only for gen1 HW
81 - mediatek,mt2701-smi-common
94 - if: # for gen2 HW that have gals
98 - mediatek,mt6779-smi-common
99 - mediatek,mt8183-smi-common
100 - mediatek,mt8192-smi-common
115 else: # for gen2 HW that don't have gals
126 additionalProperties: false
130 #include <dt-bindings/clock/mt8173-clk.h>
131 #include <dt-bindings/power/mt8173-power.h>
133 smi_common: smi@14022000 {
134 compatible = "mediatek,mt8173-smi-common";
135 reg = <0x14022000 0x1000>;
136 power-domains = <&scpsys MT8173_POWER_DOMAIN_MM>;
137 clocks = <&mmsys CLK_MM_SMI_COMMON>,
138 <&mmsys CLK_MM_SMI_COMMON>;
139 clock-names = "apb", "smi";