Documentation/devicetree/bindings/media/nxp,imx8-jpeg.yaml

   1 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/nxp,imx8-jpeg.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: i.MX8QXP/QM JPEG decoder/encoder Device Tree Bindings
   8
   9 maintainers:
  10   - Mirela Rabulea <mirela.rabulea@nxp.com>
  11
  12 description: |-
  13   The JPEG decoder/encoder present in iMX8QXP and iMX8QM SoCs is an
  14   ISO/IEC 10918-1 JPEG standard compliant decoder/encoder, for Baseline
  15   and Extended Sequential DCT modes.
  16
  17 properties:
  18   compatible:
  19     oneOf:
  20       - items:
  21           enum:
  22             - nxp,imx8qxp-jpgdec
  23             - nxp,imx8qxp-jpgenc
  24       - items:
  25           - const: nxp,imx8qm-jpgdec
  26           - const: nxp,imx8qxp-jpgdec
  27       - items:
  28           - const: nxp,imx8qm-jpgenc
  29           - const: nxp,imx8qxp-jpgenc
  30
  31   reg:
  32     maxItems: 1
  33
  34   interrupts:
  35     description: |
  36       There are 4 slots available in the IP, which the driver may use
  37       If a certain slot is used, it should have an associated interrupt
  38       The interrupt with index i is assumed to be for slot i
  39     minItems: 1               # At least one slot is needed by the driver
  40     maxItems: 4               # The IP has 4 slots available for use
  41
  42   power-domains:
  43     description:
  44       List of phandle and PM domain specifier as documented in
  45       Documentation/devicetree/bindings/power/power_domain.txt
  46     minItems: 2               # Wrapper and 1 slot
  47     maxItems: 5               # Wrapper and 4 slots
  48
  49 required:
  50   - compatible
  51   - reg
  52   - interrupts
  53   - power-domains
  54
  55 additionalProperties: false
  56
  57 examples:
  58   - |
  59     #include <dt-bindings/interrupt-controller/arm-gic.h>
  60     #include <dt-bindings/firmware/imx/rsrc.h>
  61
  62     jpegdec: jpegdec@58400000 {
  63         compatible = "nxp,imx8qxp-jpgdec";
  64         reg = <0x58400000 0x00050000 >;
  65         interrupts = <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>,
  66                      <GIC_SPI 310 IRQ_TYPE_LEVEL_HIGH>,
  67                      <GIC_SPI 311 IRQ_TYPE_LEVEL_HIGH>,
  68                      <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>;
  69         power-domains = <&pd IMX_SC_R_MJPEG_DEC_MP>,
  70                         <&pd IMX_SC_R_MJPEG_DEC_S0>,
  71                         <&pd IMX_SC_R_MJPEG_DEC_S1>,
  72                         <&pd IMX_SC_R_MJPEG_DEC_S2>,
  73                         <&pd IMX_SC_R_MJPEG_DEC_S3>;
  74     };
  75
  76     jpegenc: jpegenc@58450000 {
  77         compatible = "nxp,imx8qm-jpgenc", "nxp,imx8qxp-jpgenc";
  78         reg = <0x58450000 0x00050000 >;
  79         interrupts = <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>,
  80                      <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>,
  81                      <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>,
  82                      <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>;
  83         power-domains = <&pd IMX_SC_R_MJPEG_ENC_MP>,
  84                         <&pd IMX_SC_R_MJPEG_ENC_S0>,
  85                         <&pd IMX_SC_R_MJPEG_ENC_S1>,
  86                         <&pd IMX_SC_R_MJPEG_ENC_S2>,
  87                         <&pd IMX_SC_R_MJPEG_ENC_S3>;
  88     };
  89 ...