Documentation/devicetree/bindings/media/nxp,imx7-mipi-csi2.yaml

   1 # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
   2 %YAML 1.2
   3 ---
   4 $id: http://devicetree.org/schemas/media/nxp,imx7-mipi-csi2.yaml#
   5 $schema: http://devicetree.org/meta-schemas/core.yaml#
   6
   7 title: NXP i.MX7 and i.MX8 MIPI CSI-2 receiver
   8
   9 maintainers:
  10   - Rui Miguel Silva <rmfrfs@gmail.com>
  11   - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
  12
  13 description: |-
  14   The NXP i.MX7 and i.MX8 families contain SoCs that include a MIPI CSI-2
  15   receiver IP core named CSIS. The IP core originates from Samsung, and may be
  16   compatible with some of the Exynos4 and S5P SoCs. i.MX7 SoCs use CSIS version
  17   3.3, and i.MX8 SoCs use CSIS version 3.6.3.
  18
  19   While the CSI-2 receiver is separate from the MIPI D-PHY IP core, the PHY is
  20   completely wrapped by the CSIS and doesn't expose a control interface of its
  21   own. This binding thus covers both IP cores.
  22
  23 properties:
  24   compatible:
  25     enum:
  26       - fsl,imx7-mipi-csi2
  27       - fsl,imx8mm-mipi-csi2
  28
  29   reg:
  30     maxItems: 1
  31
  32   interrupts:
  33     maxItems: 1
  34
  35   clocks:
  36     minItems: 3
  37     items:
  38       - description: The peripheral clock (a.k.a. APB clock)
  39       - description: The external clock (optionally used as the pixel clock)
  40       - description: The MIPI D-PHY clock
  41       - description: The AXI clock
  42
  43   clock-names:
  44     minItems: 3
  45     items:
  46       - const: pclk
  47       - const: wrap
  48       - const: phy
  49       - const: axi
  50
  51   power-domains:
  52     maxItems: 1
  53
  54   phy-supply:
  55     description: The MIPI D-PHY digital power supply
  56
  57   resets:
  58     items:
  59       - description: MIPI D-PHY slave reset
  60
  61   clock-frequency:
  62     description: The desired external clock ("wrap") frequency, in Hz
  63     default: 166000000
  64
  65   ports:
  66     $ref: /schemas/graph.yaml#/properties/ports
  67
  68     properties:
  69       port@0:
  70         $ref: /schemas/graph.yaml#/$defs/port-base
  71         unevaluatedProperties: false
  72         description:
  73           Input port node, single endpoint describing the CSI-2 transmitter.
  74
  75         properties:
  76           endpoint:
  77             $ref: video-interfaces.yaml#
  78             unevaluatedProperties: false
  79
  80             properties:
  81               data-lanes:
  82                 items:
  83                   minItems: 1
  84                   maxItems: 4
  85                   items:
  86                     - const: 1
  87                     - const: 2
  88                     - const: 3
  89                     - const: 4
  90
  91             required:
  92               - data-lanes
  93
  94             allOf:
  95               - if:
  96                   properties:
  97                     compatible:
  98                       contains:
  99                         const: fsl,imx7-mipi-csi2
 100                 then:
 101                   properties:
 102                     data-lanes:
 103                       items:
 104                         maxItems: 2
 105
 106       port@1:
 107         $ref: /schemas/graph.yaml#/properties/port
 108         description:
 109           Output port node
 110
 111 required:
 112   - compatible
 113   - reg
 114   - interrupts
 115   - clocks
 116   - clock-names
 117   - power-domains
 118   - ports
 119
 120 additionalProperties: false
 121
 122 allOf:
 123   - if:
 124       properties:
 125         compatible:
 126           contains:
 127             const: fsl,imx7-mipi-csi2
 128     then:
 129       required:
 130         - phy-supply
 131         - resets
 132     else:
 133       properties:
 134         clocks:
 135           minItems: 4
 136         clock-names:
 137           minItems: 4
 138         phy-supply: false
 139         resets: false
 140
 141 examples:
 142   - |
 143     #include <dt-bindings/clock/imx7d-clock.h>
 144     #include <dt-bindings/interrupt-controller/arm-gic.h>
 145     #include <dt-bindings/interrupt-controller/irq.h>
 146     #include <dt-bindings/reset/imx7-reset.h>
 147
 148     mipi-csi@30750000 {
 149         compatible = "fsl,imx7-mipi-csi2";
 150         reg = <0x30750000 0x10000>;
 151         interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
 152
 153         clocks = <&clks IMX7D_IPG_ROOT_CLK>,
 154                  <&clks IMX7D_MIPI_CSI_ROOT_CLK>,
 155                  <&clks IMX7D_MIPI_DPHY_ROOT_CLK>;
 156         clock-names = "pclk", "wrap", "phy";
 157         clock-frequency = <166000000>;
 158
 159         power-domains = <&pgc_mipi_phy>;
 160         phy-supply = <&reg_1p0d>;
 161         resets = <&src IMX7_RESET_MIPI_PHY_MRST>;
 162
 163         ports {
 164             #address-cells = <1>;
 165             #size-cells = <0>;
 166
 167             port@0 {
 168                 reg = <0>;
 169
 170                 mipi_from_sensor: endpoint {
 171                     remote-endpoint = <&ov2680_to_mipi>;
 172                     data-lanes = <1>;
 173                 };
 174             };
 175
 176             port@1 {
 177                 reg = <1>;
 178
 179                 mipi_vc0_to_csi_mux: endpoint {
 180                     remote-endpoint = <&csi_mux_from_mipi_vc0>;
 181                 };
 182             };
 183         };
 184     };
 185
 186   - |
 187     #include <dt-bindings/clock/imx8mm-clock.h>
 188     #include <dt-bindings/interrupt-controller/arm-gic.h>
 189     #include <dt-bindings/interrupt-controller/irq.h>
 190
 191     mipi-csi@32e30000 {
 192         compatible = "fsl,imx8mm-mipi-csi2";
 193         reg = <0x32e30000 0x1000>;
 194         interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 195         clock-frequency = <333000000>;
 196         clocks = <&clk IMX8MM_CLK_DISP_APB_ROOT>,
 197                  <&clk IMX8MM_CLK_CSI1_ROOT>,
 198                  <&clk IMX8MM_CLK_CSI1_PHY_REF>,
 199                  <&clk IMX8MM_CLK_DISP_AXI_ROOT>;
 200         clock-names = "pclk", "wrap", "phy", "axi";
 201         power-domains = <&mipi_pd>;
 202
 203         ports {
 204             #address-cells = <1>;
 205             #size-cells = <0>;
 206
 207             port@0 {
 208                 reg = <0>;
 209
 210                 imx8mm_mipi_csi_in: endpoint {
 211                     remote-endpoint = <&imx477_out>;
 212                     data-lanes = <1 2 3 4>;
 213                 };
 214             };
 215
 216             port@1 {
 217                 reg = <1>;
 218
 219                 imx8mm_mipi_csi_out: endpoint {
 220                     remote-endpoint = <&csi_in>;
 221                 };
 222             };
 223         };
 224     };
 225
 226 ...