4 The OMAP mailbox hardware facilitates communication between different processors
5 using a queued mailbox interrupt mechanism. The IP block is external to the
6 various processor subsystems and is connected on an interconnect bus. The
7 communication is achieved through a set of registers for message storage and
8 interrupt configuration registers.
10 Each mailbox IP block/cluster has a certain number of h/w fifo queues and output
11 interrupt lines. An output interrupt line is routed to an interrupt controller
12 within a processor subsystem, and there can be more than one line going to a
13 specific processor's interrupt controller. The interrupt line connections are
14 fixed for an instance and are dictated by the IP integration into the SoC
15 (excluding the SoCs that have a Interrupt Crossbar IP). Each interrupt line is
16 programmable through a set of interrupt configuration registers, and have a rx
17 and tx interrupt source per h/w fifo. Communication between different processors
18 is achieved through the appropriate programming of the rx and tx interrupt
19 sources on the appropriate interrupt lines.
21 The number of h/w fifo queues and interrupt lines dictate the usable registers.
22 All the current OMAP SoCs except for the newest DRA7xx SoC has a single IP
23 instance. DRA7xx has multiple instances with different number of h/w fifo queues
24 and interrupt lines between different instances. The interrupt lines can also be
25 routed to different processor sub-systems on DRA7xx as they are routed through
26 the Crossbar, a kind of interrupt router/multiplexer. The K3 AM65x and J721E
27 SoCs has each of these instances form a cluster and combine multiple clusters
28 into a single IP block present within the Main NavSS. The interrupt lines from
29 all these clusters are multiplexed and routed to different processor subsystems
30 over a limited number of common interrupt output lines of an Interrupt Router.
31 The AM64x SoCS also uses a single IP block comprising of multiple clusters,
32 but the number of clusters are smaller, and the interrupt output lines are
33 connected directly to various processors.
37 A Mailbox device node is used to represent a Mailbox IP instance/cluster within
38 a SoC. The sub-mailboxes are represented as child nodes of this parent node.
42 - compatible: Should be one of the following,
43 "ti,omap2-mailbox" for OMAP2420, OMAP2430 SoCs
44 "ti,omap3-mailbox" for OMAP3430, OMAP3630 SoCs
45 "ti,omap4-mailbox" for OMAP44xx, OMAP54xx, AM33xx,
46 AM43xx and DRA7xx SoCs
47 "ti,am654-mailbox" for K3 AM65x and J721E SoCs
48 "ti,am64-mailbox" for K3 AM64x SoCs
49 - reg: Contains the mailbox register address range (base
51 - interrupts: Contains the interrupt information for the mailbox
52 device. The format is dependent on which interrupt
53 controller the Mailbox device uses
54 - #mbox-cells: Common mailbox binding property to identify the number
55 of cells required for the mailbox specifier. Should be
57 - ti,mbox-num-users: Number of targets (processor devices) that the mailbox
59 - ti,mbox-num-fifos: Number of h/w fifo queues within the mailbox IP block
61 SoC-specific Required properties:
62 ---------------------------------
63 The following are mandatory properties for the OMAP architecture based SoCs
65 - ti,hwmods: Name of the hwmod associated with the mailbox. This
66 should be defined in the mailbox node only if the node
67 is not defined as a child node of a corresponding sysc
70 The following are mandatory properties for the K3 AM65x and J721E SoCs only:
71 - interrupt-parent: Should contain a phandle to the TI-SCI interrupt
72 controller node that is used to dynamically program
73 the interrupt routes between the IP and the main GIC
74 controllers. See the following binding for additional
76 Documentation/devicetree/bindings/interrupt-controller/ti,sci-intr.yaml
80 A child node is used for representing the actual sub-mailbox device that is
81 used for the communication between the host processor and a remote processor.
82 Each child node should have a unique node name across all the different
87 - ti,mbox-tx: sub-mailbox descriptor property defining a Tx fifo
88 - ti,mbox-rx: sub-mailbox descriptor property defining a Rx fifo
90 Sub-mailbox Descriptor Data
91 ---------------------------
92 Each of the above ti,mbox-tx and ti,mbox-rx properties should have 3 cells of
93 data that represent the following:
94 Cell #1 (fifo_id) - mailbox fifo id used either for transmitting
95 (ti,mbox-tx) or for receiving (ti,mbox-rx)
96 Cell #2 (irq_id) - irq identifier index number to use from the parent's
97 interrupts data. Should be 0 for most of the cases, a
98 positive index value is seen only on mailboxes that have
99 multiple interrupt lines connected to the MPU processor.
100 Cell #3 (usr_id) - mailbox user id for identifying the interrupt line
101 associated with generating a tx/rx fifo interrupt.
105 - ti,mbox-send-noirq: Quirk flag to allow the client user of this sub-mailbox
106 to send messages without triggering a Tx ready interrupt,
107 and to control the Tx ticker. Should be used only on
108 sub-mailboxes used to communicate with WkupM3 remote
109 processor on AM33xx/AM43xx SoCs.
113 A device needing to communicate with a target processor device should specify
114 them using the common mailbox binding properties, "mboxes" and the optional
115 "mbox-names" (please see Documentation/devicetree/bindings/mailbox/mailbox.txt
116 for details). Each value of the mboxes property should contain a phandle to the
117 mailbox controller device node and an args specifier that will be the phandle to
118 the intended sub-mailbox child node to be used for communication. The equivalent
119 "mbox-names" property value can be used to give a name to the communication channel
120 to be used by the client user.
127 mailbox: mailbox@4a0f4000 {
128 compatible = "ti,omap4-mailbox";
129 reg = <0x4a0f4000 0x200>;
130 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
131 ti,hwmods = "mailbox";
133 ti,mbox-num-users = <3>;
134 ti,mbox-num-fifos = <8>;
136 ti,mbox-tx = <0 0 0>;
137 ti,mbox-rx = <1 0 0>;
140 ti,mbox-tx = <3 0 0>;
141 ti,mbox-rx = <2 0 0>;
147 mboxes = <&mailbox &mbox_dsp>;
152 mailbox: mailbox@480c8000 {
153 compatible = "ti,omap4-mailbox";
154 reg = <0x480C8000 0x200>;
156 ti,hwmods = "mailbox";
158 ti,mbox-num-users = <4>;
159 ti,mbox-num-fifos = <8>;
160 mbox_wkupm3: wkup_m3 {
161 ti,mbox-tx = <0 0 0>;
162 ti,mbox-rx = <0 0 3>;
168 cbass_main_navss: interconnect0 {
169 mailbox0_cluster0: mailbox@31f80000 {
170 compatible = "ti,am654-mailbox";
171 reg = <0x00 0x31f80000 0x00 0x200>;
173 ti,mbox-num-users = <4>;
174 ti,mbox-num-fifos = <16>;
175 interrupt-parent = <&intr_main_navss>;
176 interrupts = <164 0>;
178 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 {
179 ti,mbox-tx = <1 0 0>;
180 ti,mbox-rx = <0 0 0>;